公开(公告)号：US10347761B2

公开(公告)日：2019-07-09

申请号：US15821860

申请日：2017-11-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Chun-Jung Tang ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L21/762 ,  H01L29/08 ,  H01L29/66 ,  H01L29/165 ,  H01L29/167

Abstract: A tunnel field effect transistor (TFET) includes: a first gate structure on a substrate; a source region having a first conductive type on one side of the first gate structure; a drain region having a second conductive type on another side of the first gate structure; a first isolation structure adjacent to the source region; and a second isolation structure adjacent to the drain region. Preferably, the first isolation and the second isolation comprise different material and different depths or same material and different depths.

公开(公告)号：US20160225880A1

公开(公告)日：2016-08-04

申请号：US15092623

申请日：2016-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kung-Hong Lee ,  Chun-Jung Tang ,  Te-Chih Chen ,  Tai-Ju Chen

IPC: H01L29/66 ,  H01L29/161 ,  H01L29/16 ,  H01L29/24 ,  H01L29/78 ,  H01L29/167

CPC classification number: H01L29/66795 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/24 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785

Abstract: The present invention provides a method of forming a metal oxide semiconductor (MOS) device comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and a part thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.

Abstract translation: 本发明提供一种形成包括栅极结构和外延结构的金属氧化物半导体（MOS）器件的方法。 栅极结构设置在基板上。 外延结构在栅极结构的两侧设置在衬底中，其一部分用作MOS的源极/漏极，其中外延结构包括：具有第二导电类型的第一缓冲层，第二缓冲层和 具有与第二导电类型互补的第一导电类型的外延层。 本发明还提供一种形成该方法的方法。

公开(公告)号：US11227769B2

公开(公告)日：2022-01-18

申请号：US16833685

申请日：2020-03-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Jung Tang ,  Yu-Jen Liu

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/49

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming an interlayer dielectric (ILD) layer around the gate structure; performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate; forming an inter-metal dielectric (IMD) layer on the metal gate; forming a metal interconnection in the IMD layer; and performing a high pressure anneal (HPA) process for improving work function variation of the metal gate.

公开(公告)号：US09741830B2

公开(公告)日：2017-08-22

申请号：US15092623

申请日：2016-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kung-Hong Lee ,  Chun-Jung Tang ,  Te-Chih Chen ,  Tai-Ju Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/24 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/24 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785

Abstract: The present invention provides a method of forming a metal oxide semiconductor (MOS) device comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and a part thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.

公开(公告)号：US20190131453A1

公开(公告)日：2019-05-02

申请号：US15821860

申请日：2017-11-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Chun-Jung Tang ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L21/762

CPC classification number: H01L29/7846 ,  H01L21/76224 ,  H01L21/76229 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/167 ,  H01L29/42356 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7848 ,  H01L29/7851

Abstract: A tunnel field effect transistor (TFET) includes: a first gate structure on a substrate; a source region having a first conductive type on one side of the first gate structure; a drain region having a second conductive type on another side of the first gate structure; a first isolation structure adjacent to the source region; and a second isolation structure adjacent to the drain region. Preferably, the first isolation and the second isolation comprise different material and different depths or same material and different depths.

公开(公告)号：US20160155837A1

公开(公告)日：2016-06-02

申请号：US14583600

申请日：2014-12-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kung-Hong Lee ,  Chun-Jung Tang ,  Te-Chih Chen ,  Tai-Ju Chen

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/24 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785

Abstract: The present invention provides a metal oxide semiconductor (MOS) device, comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and apart thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.

Abstract translation: 本发明提供了一种包括栅极结构和外延结构的金属氧化物半导体（MOS）器件。 栅极结构设置在基板上。 所述外延结构在所述栅极结构的两侧设置在所述衬底中，并且所述外延结构用作所述MOS的源极/漏极，其中所述外延结构包括：具有第二导电类型的第一缓冲层，第二缓冲层和 具有与第二导电类型互补的第一导电类型的外延层。 本发明还提供一种形成该方法的方法。

公开(公告)号：US20210272813A1

公开(公告)日：2021-09-02

申请号：US16833685

申请日：2020-03-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Jung Tang ,  Yu-Jen Liu

IPC: H01L21/28 ,  H01L29/66

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming an interlayer dielectric (ILD) layer around the gate structure; performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate; forming an inter-metal dielectric (IMD) layer on the metal gate; forming a metal interconnection in the IMD layer; and performing a high pressure anneal (HPA) process for improving work function variation of the metal gate.

公开(公告)号：US09337339B1

公开(公告)日：2016-05-10

申请号：US14583600

申请日：2014-12-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kung-Hong Lee ,  Chun-Jung Tang ,  Te-Chih Chen ,  Tai-Ju Chen

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/24 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785

Abstract: The present invention provides a metal oxide semiconductor (MOS) device, comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and apart thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.

Abstract translation: 本发明提供了一种包括栅极结构和外延结构的金属氧化物半导体（MOS）器件。 栅极结构设置在基板上。 所述外延结构在所述栅极结构的两侧设置在所述衬底中，并且所述外延结构用作所述MOS的源极/漏极，其中所述外延结构包括：具有第二导电类型的第一缓冲层，第二缓冲层和 具有与第二导电类型互补的第一导电类型的外延层。 本发明还提供一种形成该方法的方法。