公开(公告)号：US12245519B2

公开(公告)日：2025-03-04

申请号：US18542791

申请日：2023-12-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chang Hsu ,  Tang-Chun Weng ,  Cheng-Yi Lin ,  Yung-Shen Chen ,  Chia-Hung Lin

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.

公开(公告)号：US20240122078A1

公开(公告)日：2024-04-11

申请号：US18542791

申请日：2023-12-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chang Hsu ,  Tang-Chun Weng ,  Cheng-Yi Lin ,  Yung-Shen Chen ,  Chia-Hung Lin

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.

公开(公告)号：US11895927B2

公开(公告)日：2024-02-06

申请号：US17319106

申请日：2021-05-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chang Hsu ,  Tang-Chun Weng ,  Cheng-Yi Lin ,  Yung-Shen Chen ,  Chia-Hung Lin

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.

公开(公告)号：US20220344579A1

公开(公告)日：2022-10-27

申请号：US17319106

申请日：2021-05-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chang Hsu ,  Tang-Chun Weng ,  Cheng-Yi Lin ,  Yung-Shen Chen ,  Chia-Hung Lin

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.