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公开(公告)号：US20220367565A1
公开(公告)日：2022-11-17
申请号：US17345806
申请日：2021-06-11
发明人： Cheng-Yi Lin , Tang Chun Weng , Chia-Chang Hsu , Yung Shen Chen , Chia-Hung Lin
IPC分类号： H01L27/22 , H01L23/522 , H01L23/528 , H01L43/12 , H01L43/02
摘要： Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.
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公开(公告)号：US20230262993A1
公开(公告)日：2023-08-17
申请号：US18304335
申请日：2023-04-20
发明人： Cheng-Yi Lin , Tang Chun Weng , Chia-Chang Hsu , Yung Shen Chen , Chia-Hung Lin
IPC分类号： H10B61/00 , H01L23/522 , H01L23/528 , H10N50/01 , H10N50/80
CPC分类号： H10B61/00 , H01L23/5226 , H01L23/5283 , H10N50/01 , H10N50/80
摘要： Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.
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公开(公告)号：US11690230B2
公开(公告)日：2023-06-27
申请号：US17345806
申请日：2021-06-11
发明人： Cheng-Yi Lin , Tang Chun Weng , Chia-Chang Hsu , Yung Shen Chen , Chia-Hung Lin
IPC分类号： H10B61/00 , H01L23/522 , H01L23/528 , H10N50/01 , H10N50/80
CPC分类号： H10B61/00 , H01L23/5226 , H01L23/5283 , H10N50/01 , H10N50/80
摘要： Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.
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公开(公告)号：US12089419B2
公开(公告)日：2024-09-10
申请号：US18304335
申请日：2023-04-20
发明人： Cheng-Yi Lin , Tang Chun Weng , Chia-Chang Hsu , Yung Shen Chen , Chia-Hung Lin
IPC分类号： H10B61/00 , H01L23/522 , H01L23/528 , H10N50/01 , H10N50/80
CPC分类号： H10B61/00 , H01L23/5226 , H01L23/5283 , H10N50/01 , H10N50/80
摘要： Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.
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公开(公告)号：US20240122078A1
公开(公告)日：2024-04-11
申请号：US18542791
申请日：2023-12-18
发明人： Chia-Chang Hsu , Tang-Chun Weng , Cheng-Yi Lin , Yung-Shen Chen , Chia-Hung Lin
摘要： A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.
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公开(公告)号：US11895927B2
公开(公告)日：2024-02-06
申请号：US17319106
申请日：2021-05-13
发明人： Chia-Chang Hsu , Tang-Chun Weng , Cheng-Yi Lin , Yung-Shen Chen , Chia-Hung Lin
摘要： A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.
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公开(公告)号：US20220344579A1
公开(公告)日：2022-10-27
申请号：US17319106
申请日：2021-05-13
发明人： Chia-Chang Hsu , Tang-Chun Weng , Cheng-Yi Lin , Yung-Shen Chen , Chia-Hung Lin
摘要： A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.
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