公开(公告)号：US20140146610A1

公开(公告)日：2014-05-29

申请号：US13685719

申请日：2012-11-27

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Shi-Wen CHEN ,  Chi-Chang SHUAI ,  Chung-Cheng TSAI ,  Ya-Nan MOU

IPC: G11C16/30

CPC classification number: G11C16/30

Abstract: An operation method of a memory includes the following steps: determining the number of memory units required to update the content stored therein when the memory is performing a program operation based on the N-bit input data and accordingly generate a first determination result; and providing (N−M) number of loads to a source line decoder of the memory if the first determination result indicates that there are M number of memory units required to update the content stored therein, and thereby coupling the (N−M) number of the provided loads to a transmission path of a power supply voltage in parallel, wherein N and M are natural numbers. A memory is also provided.

Abstract translation: 存储器的操作方法包括以下步骤：当存储器基于N位输入数据执行编程操作时，确定更新存储在其中的内容所需的存储器单元的数量，从而产生第一确定结果; 并且如果第一确定结果指示存在M个存储器单元所需的更新存储在其中的内容，从而将（N-M）数量的负载提供给存储器的源线解码器，从而将（N-M）个数量 将所提供的负载并联到电源电压的传输路径，其中N和M是自然数。 还提供了一个记忆。

公开(公告)号：US20140140120A1

公开(公告)日：2014-05-22

申请号：US13682742

申请日：2012-11-21

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Hsin-Wen CHEN ,  Chi-Chang SHUAI ,  Shih-Chin LIN

IPC: G11C5/06

CPC classification number: G11C5/06 ,  G11C8/14 ,  G11C11/418

Abstract: A memory cell includes six transistors. The first and second P-type transistors have the sources coupled to a first voltage. The first and second N-type transistors have the drains coupled to drains of the first and second P-type transistors, respectively; the sources coupled to a second voltage; and the gates coupled to gates of the first and second P-type transistors, respectively. The third N-type transistor has the drain coupled to a write word line; the source coupled to drain of the first N-type transistor and gate of the second N-type transistor; and the gate coupled to a first write bit line. The fourth N-type transistor has the drain coupled to the write word line; the source coupled to drain of the second N-type transistor and gate of the first N-type transistor; and the gate coupled to a second write bit line. A memory cell array is also provided.

Abstract translation: 存储单元包括六个晶体管。 第一和第二P型晶体管具有耦合到第一电压的源极。 第一和第二N型晶体管分别具有耦合到第一和第二P型晶体管的漏极的漏极; 所述源耦合到第二电压; 并且分别与第一和第二P型晶体管的栅极耦合的栅极。 第三N型晶体管具有耦合到写字线的漏极; 源极耦合到第一N型晶体管的漏极和第二N型晶体管的栅极; 并且栅极耦合到第一写入位线。 第四N型晶体管具有耦合到写字线的漏极; 所述源极耦合到所述第二N型晶体管的漏极和所述第一N型晶体管的栅极; 并且栅极耦合到第二写入位线。 还提供了存储单元阵列。