公开(公告)号：US20140211573A1

公开(公告)日：2014-07-31

申请号：US14225435

申请日：2014-03-26

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Shi-Wen CHEN ,  Hsin-Pang LU ,  Chung-Cheng TSAI ,  Ya-Nan MOU

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C7/00 ,  G11C7/08 ,  G11C7/10 ,  G11C8/08 ,  G11C11/4074 ,  G11C16/30 ,  G11C29/021

Abstract: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.

Abstract translation: 电源电压产生电路包括比较单元，电压电平控制单元和电压调节器电路。 比较单元被配置为将存储器阵列的输入数据和输出数据彼此进行比较，从而生成比较结果，其中输出数据是存储在存储器阵列的多个存储器单元中的存储数据，该存储器单元根据根据 输入数据和比较结果表示输出数据和输入数据之间存在的不同位数。 电压电平控制单元被配置为根据比较结果产生控制信号。 电压调节器电路被配置为为存储器阵列提供电源电压，并根据控制信号调整电源电压的值。 还提供了用于存储器阵列的供应生成电路的存储器和操作方法。

公开(公告)号：US20140146610A1

公开(公告)日：2014-05-29

申请号：US13685719

申请日：2012-11-27

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Shi-Wen CHEN ,  Chi-Chang SHUAI ,  Chung-Cheng TSAI ,  Ya-Nan MOU

IPC: G11C16/30

CPC classification number: G11C16/30

Abstract: An operation method of a memory includes the following steps: determining the number of memory units required to update the content stored therein when the memory is performing a program operation based on the N-bit input data and accordingly generate a first determination result; and providing (N−M) number of loads to a source line decoder of the memory if the first determination result indicates that there are M number of memory units required to update the content stored therein, and thereby coupling the (N−M) number of the provided loads to a transmission path of a power supply voltage in parallel, wherein N and M are natural numbers. A memory is also provided.

Abstract translation: 存储器的操作方法包括以下步骤：当存储器基于N位输入数据执行编程操作时，确定更新存储在其中的内容所需的存储器单元的数量，从而产生第一确定结果; 并且如果第一确定结果指示存在M个存储器单元所需的更新存储在其中的内容，从而将（N-M）数量的负载提供给存储器的源线解码器，从而将（N-M）个数量 将所提供的负载并联到电源电压的传输路径，其中N和M是自然数。 还提供了一个记忆。