公开(公告)号：US20150048486A1

公开(公告)日：2015-02-19

申请号：US13968392

申请日：2013-08-15

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Hung-Lin Shih ,  Chih-Chien Liu ,  Jei-Ming Chen ,  Wen-Yi Teng ,  Chieh-Wen Lo

IPC: H01L21/308 ,  H01L29/06

CPC classification number: H01L29/0692 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/308 ,  H01L21/823821 ,  H01L29/06 ,  H01L29/66795

Abstract: A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening.

Abstract translation: 制造空间半导体结构的方法包括以下步骤。 首先，提供半导体衬底。 然后，在半导体衬底上形成第一掩模层。 然后，在第一掩模层中至少形成第一开口并暴露半导体衬底的一部分表面。 然后，在第一开口中形成第一半导体图形。 然后，在第一半导体图案和第一掩模层上形成第二掩模层。 然后，通过第二掩模层形成至少第二开口到第一掩模层，并暴露半导体衬底的表面的另一部分。 并且，在第二开口中形成第二半导体图案。

公开(公告)号：US09362358B2

公开(公告)日：2016-06-07

申请号：US14792638

申请日：2015-07-07

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Hung-Lin Shih ,  Chih-Chien Liu ,  Jei-Ming Chen ,  Wen-Yi Teng ,  Chieh-Wen Lo

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/308 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/0692 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/308 ,  H01L21/823821 ,  H01L29/06 ,  H01L29/66795

Abstract: A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening.

Abstract translation: 制造空间半导体结构的方法包括以下步骤。 首先，提供半导体衬底。 然后，在半导体衬底上形成第一掩模层。 然后，在第一掩模层中至少形成第一开口并暴露半导体衬底的一部分表面。 然后，在第一开口中形成第一半导体图形。 然后，在第一半导体图案和第一掩模层上形成第二掩模层。 然后，通过第二掩模层形成至少第二开口到第一掩模层，并暴露半导体衬底的表面的另一部分。 并且，在第二开口中形成第二半导体图案。

公开(公告)号：US09105582B2

公开(公告)日：2015-08-11

申请号：US13968392

申请日：2013-08-15

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Hung-Lin Shih ,  Chih-Chien Liu ,  Jei-Ming Chen ,  Wen-Yi Teng ,  Chieh-Wen Lo

IPC: H01L21/76 ,  H01L29/06 ,  H01L21/308

CPC classification number: H01L29/0692 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/308 ,  H01L21/823821 ,  H01L29/06 ,  H01L29/66795

Abstract: A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening.

Abstract translation: 制造空间半导体结构的方法包括以下步骤。 首先，提供半导体衬底。 然后，在半导体衬底上形成第一掩模层。 然后，在第一掩模层中至少形成第一开口并暴露半导体衬底的一部分表面。 然后，在第一开口中形成第一半导体图形。 然后，在第一半导体图案和第一掩模层上形成第二掩模层。 然后，通过第二掩模层形成至少第二开口到第一掩模层，并暴露半导体衬底的表面的另一部分。 并且，在第二开口中形成第二半导体图案。