公开(公告)号：US08711598B1

公开(公告)日：2014-04-29

申请号：US13682742

申请日：2012-11-21

Applicant: United Microelectronics Corporation

Inventor： Hsin-Wen Chen ,  Chi-Chang Shuai ,  Shih-Chin Lin

IPC: G11C5/06

CPC classification number: G11C5/06 ,  G11C8/14 ,  G11C11/418

Abstract: A memory cell includes six transistors. The first and second P-type transistors have the sources coupled to a first voltage. The first and second N-type transistors have the drains coupled to drains of the first and second P-type transistors, respectively; the sources coupled to a second voltage; and the gates coupled to gates of the first and second P-type transistors, respectively. The third N-type transistor has the drain coupled to a write word line; the source coupled to drain of the first N-type transistor and gate of the second N-type transistor; and the gate coupled to a first write bit line. The fourth N-type transistor has the drain coupled to the write word line; the source coupled to drain of the second N-type transistor and gate of the first N-type transistor; and the gate coupled to a second write bit line. A memory cell array is also provided.

Abstract translation: 存储单元包括六个晶体管。 第一和第二P型晶体管具有耦合到第一电压的源极。 第一和第二N型晶体管分别具有耦合到第一和第二P型晶体管的漏极的漏极; 所述源耦合到第二电压; 并且分别与第一和第二P型晶体管的栅极耦合的栅极。 第三N型晶体管具有耦合到写字线的漏极; 源极耦合到第一N型晶体管的漏极和第二N型晶体管的栅极; 并且栅极耦合到第一写入位线。 第四N型晶体管具有耦合到写字线的漏极; 所述源极耦合到所述第二N型晶体管的漏极和所述第一N型晶体管的栅极; 并且栅极耦合到第二写入位线。 还提供了存储单元阵列。

公开(公告)号：US09571079B2

公开(公告)日：2017-02-14

申请号：US14938827

申请日：2015-11-11

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Yu-Yee Liow ,  Ya-Nan Mou ,  Yuan-Hui Chen ,  Shih-Chin Lin ,  Po-Hua Chen ,  Wen-Hong Hsu

IPC: H03H11/26 ,  H03K5/13 ,  G01R19/00 ,  H03K5/00

CPC classification number: H03K5/133 ,  G01R19/0084 ,  H03K2005/00019

Abstract: An integrated circuit includes a signal generating unit, a signal monitoring unit and a processing unit. The signal generating unit is configured to generate a control signal. The signal monitoring unit is configured to receive the control signal and accordingly output a monitor signal. The processing unit is configured to receive the monitor signal. The control signal is adjusted until the monitor signal is located within a preset range. A signal monitoring method used with the integrated circuit and a signal monitoring method used with a plurality of transistors are also provided.

Abstract translation: 集成电路包括信号发生单元，信号监视单元和处理单元。 信号生成单元被配置为产生控制信号。 信号监视单元被配置为接收控制信号并相应地输出监视信号。 处理单元被配置为接收监视信号。 控制信号被调整直到监视信号位于预设范围内。 还提供了与集成电路一起使用的信号监视方法以及与多个晶体管一起使用的信号监视方法。