公开(公告)号：US20160148998A1

公开(公告)日：2016-05-26

申请号：US14549523

申请日：2014-11-20

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： YEN-LIANG WU ,  CHUNG-FU CHANG ,  WEN-JIUN SHEN ,  MAN-LING LU ,  CHIA-JONG LIU ,  YI-WEI CHEN

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/7856

Abstract: A FINFET structure is provided. The FINFET structure includes a substrate, a PMOS element, a NMOS element, a STI structure, and a bump structure. The substrate includes a first area and a second area adjacent to the first area. The PMOS element is disposed in the first area of the substrate, and includes at least one first fin structure. The NMOS element is disposed in the second area of the substrate and includes at least one second fin structure. The STI structure is disposed between the first fin structure and the second fin structure. The bump structure is disposed on the STI structure and has a carbon-containing dielectric material.

Abstract translation: 提供FINFET结构。 FINFET结构包括衬底，PMOS元件，NMOS元件，STI结构和凸块结构。 基板包括与第一区域相邻的第一区域和第二区域。 PMOS元件设置在衬底的第一区域中，并且包括至少一个第一鳍结构。 NMOS元件设置在衬底的第二区域中并且包括至少一个第二鳍结构。 STI结构设置在第一翅片结构和第二翅片结构之间。 凸块结构设置在STI结构上并具有含碳介电材料。

公开(公告)号：US20160163837A1

公开(公告)日：2016-06-09

申请号：US15046467

申请日：2016-02-18

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： YEN-LIANG WU ,  CHUNG-FU CHANG ,  YU-HSIANG HUNG ,  SSU-I FU ,  WEN-JIUN SHEN ,  MAN-LING LU ,  CHIA-JONG LIU ,  YI-WEI CHEN

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/6656 ,  H01L29/785

Abstract: A field effect transistor (FinFET) device includes a substrate, a fin structure, a shallow trench isolation and a gate structure. The fin structure is formed on a surface of the substrate and includes a base fin structure and an epitaxial fin structure formed on the base fin structure. The shallow trench isolation structure is formed on the surface of the substrate and includes a peripheral zone and a concave zone. The peripheral zone physically contacts with the fin structure. The gate structure is disposed on the epitaxial fin structure perpendicularly. A method of fabricating the aforementioned field effect transistor is also provided.

Abstract translation: 场效应晶体管（FinFET）器件包括衬底，鳍结构，浅沟槽隔离和栅极结构。 翅片结构形成在基板的表面上，并且包括底鳍结构和形成在基底鳍结构上的外延翅片结构。 浅沟槽隔离结构形成在基板的表面上并且包括周边区域和凹陷区域。 周边区域与翅片结构物理接触。 栅极结构垂直地设置在外延鳍结构上。 还提供了制造上述场效应晶体管的方法。

公开(公告)号：US20160104612A1

公开(公告)日：2016-04-14

申请号：US14511092

申请日：2014-10-09

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： YI-HUI LEE ,  TSUNG-HUNG CHANG ,  CHING-WEN HUNG ,  JIA-RONG WU ,  CHING-LING LIN ,  CHIH-SEN HUANG ,  YI-WEI CHEN ,  CHIA-CHANG HSU ,  SHU-MIN HUANG ,  HSIN-FU HUANG

IPC: H01L21/02 ,  H01L21/768

CPC classification number: H01L21/76883 ,  H01L21/02057 ,  H01L21/02063 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76855

Abstract: The method for cleaning a contact hole and forming a contact plug therein is provided. The method includes steps of: providing a silicon substrate; forming a contact hole in the silicon substrate; performing a pre-cleaning process to clean the contact hole; and forming a contact plug in the contact hole. The pre-cleaning process includes steps of: performing an oxide dry etching process; performing a first thermal annealing process with a temperature which is equal to or greater than 300° C.; performing a degassing process with a temperature which is equal to or greater than 300° C.; and performing an Ar-plasma etching process.

Abstract translation: 提供了用于清洁接触孔并形成接触插塞的方法。 该方法包括以下步骤：提供硅衬底; 在硅衬底中形成接触孔; 执行预清洁处理以清洁接触孔; 并在接触孔中形成接触塞。 预清洗工艺包括以下步骤：进行氧化干蚀刻工艺; 执行温度等于或大于300℃的第一热退火工艺; 以等于或大于300℃的温度进行脱气处理; 并进行Ar等离子体蚀刻处理。

公开(公告)号：US20160049467A1

公开(公告)日：2016-02-18

申请号：US14490624

申请日：2014-09-18

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： YEN-LIANG WU ,  CHUNG-FU CHANG ,  YU-HSIANG HUNG ,  SSU-I FU ,  WEN-JIUN SHEN ,  MAN-LING LU ,  CHIA-JONG LIU ,  YI-WEI CHEN

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A field effect transistor (FinFET) device includes a substrate, a fin structure, a shallow trench isolation and a gate structure. The fin structure is formed on a surface of the substrate and includes a base fin structure and an epitaxial fin structure formed on the base fin structure. The shallow trench isolation structure is formed on the surface of the substrate and includes a peripheral zone and a concave zone. The peripheral zone physically contacts with the fin structure. The gate structure is disposed on the epitaxial fin structure perpendicularly. A method of fabricating the aforementioned field effect transistor is also provided.