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    METHOD FOR FORMING SEMICONDUCTOR DEVICE WITH LOW SEALING LOSS
    1.
    发明申请
    METHOD FOR FORMING SEMICONDUCTOR DEVICE WITH LOW SEALING LOSS 有权
    用于形成具有低密封损失的半导体器件的方法

    公开(公告)号：US20160141386A1

    公开(公告)日：2016-05-19

    申请号：US14542685

    申请日：2014-11-17

    Applicant: UNITED MICROELECTRONICS CORPORATION

    Inventor： YU-HSIANG HUNG ,  YEN-LIANG WU ,  SSU-I FU ,  CHIH-KAI HSU ,  JYH-SHYANG JENQ

    IPC: H01L29/66 ,  H01L21/266 ,  H01L21/033 ,  H01L21/02 ,  H01L21/311

    CPC classification number: H01L29/66492 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/266 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/66795

    Abstract: A method for forming a semiconductor device, includes steps of: providing a substrate; forming a first seal layer over the substrate; forming a second seal layer atop the first seal layer; forming a patterned photoresist layer on the second seal layer; implanting a dopant into the substrate by using the patterned photoresist layer as a mask; executing a first removing process to remove the patterned photoresist layer, wherein the first seal layer has a higher etch rate than that of the second seal layer in the first removing process; and removing the second seal layer after removing the patterned photoresist layer.

    Abstract translation: 一种形成半导体器件的方法，包括以下步骤：提供衬底; 在所述基底上形成第一密封层; 在所述第一密封层的顶部形成第二密封层; 在所述第二密封层上形成图案化的光致抗蚀剂层; 通过使用图案化的光致抗蚀剂层作为掩模将掺杂剂注入到衬底中; 执行第一去除过程以去除图案化的光致抗蚀剂层，其中在第一去除过程中，第一密封层具有比第二密封层的蚀刻速率更高的蚀刻速率; 以及在去除图案化的光致抗蚀剂层之后去除第二密封层。

    FINFET STRUCTURE
    2.
    发明申请
    FINFET STRUCTURE 有权
    FINFET结构

    公开(公告)号：US20160148998A1

    公开(公告)日：2016-05-26

    申请号：US14549523

    申请日：2014-11-20

    Applicant: UNITED MICROELECTRONICS CORPORATION

    Inventor： YEN-LIANG WU ,  CHUNG-FU CHANG ,  WEN-JIUN SHEN ,  MAN-LING LU ,  CHIA-JONG LIU ,  YI-WEI CHEN

    IPC: H01L29/06 ,  H01L27/092 ,  H01L29/78

    CPC classification number: H01L29/0649 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/7856

    Abstract: A FINFET structure is provided. The FINFET structure includes a substrate, a PMOS element, a NMOS element, a STI structure, and a bump structure. The substrate includes a first area and a second area adjacent to the first area. The PMOS element is disposed in the first area of the substrate, and includes at least one first fin structure. The NMOS element is disposed in the second area of the substrate and includes at least one second fin structure. The STI structure is disposed between the first fin structure and the second fin structure. The bump structure is disposed on the STI structure and has a carbon-containing dielectric material.

    Abstract translation: 提供FINFET结构。 FINFET结构包括衬底，PMOS元件，NMOS元件，STI结构和凸块结构。 基板包括与第一区域相邻的第一区域和第二区域。 PMOS元件设置在衬底的第一区域中，并且包括至少一个第一鳍结构。 NMOS元件设置在衬底的第二区域中并且包括至少一个第二鳍结构。 STI结构设置在第一翅片结构和第二翅片结构之间。 凸块结构设置在STI结构上并具有含碳介电材料。

    FIN FIELD EFFECT TRANSISTOR DEVICE AND FABRICATION METHOD THEREOF
    3.
    发明申请
    FIN FIELD EFFECT TRANSISTOR DEVICE AND FABRICATION METHOD THEREOF 有权
    FIN场效应晶体管器件及其制造方法

    公开(公告)号：US20160163837A1

    公开(公告)日：2016-06-09

    申请号：US15046467

    申请日：2016-02-18

    Applicant: UNITED MICROELECTRONICS CORPORATION

    Inventor： YEN-LIANG WU ,  CHUNG-FU CHANG ,  YU-HSIANG HUNG ,  SSU-I FU ,  WEN-JIUN SHEN ,  MAN-LING LU ,  CHIA-JONG LIU ,  YI-WEI CHEN

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

    CPC classification number: H01L29/66795 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/6656 ,  H01L29/785

    Abstract: A field effect transistor (FinFET) device includes a substrate, a fin structure, a shallow trench isolation and a gate structure. The fin structure is formed on a surface of the substrate and includes a base fin structure and an epitaxial fin structure formed on the base fin structure. The shallow trench isolation structure is formed on the surface of the substrate and includes a peripheral zone and a concave zone. The peripheral zone physically contacts with the fin structure. The gate structure is disposed on the epitaxial fin structure perpendicularly. A method of fabricating the aforementioned field effect transistor is also provided.

    Abstract translation: 场效应晶体管（FinFET）器件包括衬底，鳍结构，浅沟槽隔离和栅极结构。 翅片结构形成在基板的表面上，并且包括底鳍结构和形成在基底鳍结构上的外延翅片结构。 浅沟槽隔离结构形成在基板的表面上并且包括周边区域和凹陷区域。 周边区域与翅片结构物理接触。 栅极结构垂直地设置在外延鳍结构上。 还提供了制造上述场效应晶体管的方法。

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