公开(公告)号：US20140099760A1

公开(公告)日：2014-04-10

申请号：US14103827

申请日：2013-12-11

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chieh-Te CHEN ,  Shih-Fang TZOU ,  Jiunn-Hsiung LIAO ,  Yi-Po LIN

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/321 ,  H01L21/8232 ,  H01L21/027

CPC classification number: H01L21/28079 ,  H01L21/027 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/8232 ,  H01L27/0629

Abstract: A method for fabricating a semiconductor device, wherein the method comprises steps as follows: A dummy gate with a poly-silicon gate electrode and a passive device having a poly-silicon element layer are firstly provided. A hard mask layer is then formed on the dummy gate and the passive device. Next, a first etching process is performed to remove a portion of the hard mask layer to expose a portion of the poly-silicon element layer. Subsequently, an inner layer dielectric (ILD) is formed on the dummy gate and the poly-silicon element layer, and the ILD is flattened by using the hard mask layer as a polishing stop layer. Thereafter, a second etching process is performed to remove the poly-silicon gate electrode, and a metal gate electrode is formed on the location where the poly-silicon gate electrode was initially disposed.

Abstract translation: 一种制造半导体器件的方法，其中该方法包括以下步骤：首先提供具有多晶硅栅极的伪栅极和具有多晶硅元件层的无源器件。 然后在伪栅极和无源器件上形成硬掩模层。 接下来，执行第一蚀刻工艺以去除硬掩模层的一部分以暴露多晶硅元件层的一部分。 随后，在虚拟栅极和多晶硅元件层上形成内层电介质（ILD），并且通过使用硬掩模层作为抛光停止层使ILD变平。 此后，进行第二蚀刻处理以去除多晶硅栅电极，并且在最初设置多晶硅栅电极的位置处形成金属栅电极。