公开(公告)号：US20240385844A1

公开(公告)日：2024-11-21

申请号：US18788433

申请日：2024-07-30

Applicant: UNTETHER AI CORPORATION

Inventor： William Martin SNELGROVE ,  Darrick WIEBE

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/02 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  G06F15/78 ,  G06N3/045 ,  G06N3/063

Abstract: An example device includes a plurality of computational memory banks. Each computational memory bank of the plurality of computational memory banks includes an array of memory units and a plurality of processing elements connected to the array of memory units. The device further includes a plurality of single instruction, multiple data (SIMD) controllers. Each SIMD controller of the plurality of SIMD controllers is contained within at least one computational memory bank of the plurality of computational memory banks. Each SIMD controller is to provide instructions to the at least one computational memory bank.

公开(公告)号：US20230069360A1

公开(公告)日：2023-03-02

申请号：US17984722

申请日：2022-11-10

Applicant: UNTETHER AI CORPORATION

Inventor： William Martin SNELGROVE ,  Darrick WIEBE

IPC: G06N3/04 ,  G06F9/38 ,  G06F13/40 ,  G06N3/063

Abstract: A system and method for enhancing C*RAM, improving its performance for known applications such as video processing but also making it well suited to low-power implementation of neural nets. The required computing engine is decomposed into banks of enhanced C*RAM each having a SIMD controller, thus allowing operations at several scales simultaneously. Several configurations of suitable controllers are discussed, along with communication structures and enhanced processing elements.

公开(公告)号：US20240362456A1

公开(公告)日：2024-10-31

申请号：US18770518

申请日：2024-07-11

Applicant: UNTETHER AI CORPORATION

Inventor： William Martin SNELGROVE ,  Darrick WIEBE

IPC: G06N3/045 ,  G06F9/38 ,  G06F13/40 ,  G06N3/063

CPC classification number: G06N3/045 ,  G06F9/3887 ,  G06F13/4022 ,  G06N3/063 ,  Y02D10/00

Abstract: A system and method for enhancing C*RAM, improving its performance for known applications such as video processing but also making it well suited to low-power implementation of neural nets. The required computing engine is decomposed into banks of enhanced C*RAM each having a SIMD controller, thus allowing operations at several scales simultaneously. Several configurations of suitable controllers are discussed, along with communication structures and enhanced processing elements.