公开(公告)号：US20240419400A1

公开(公告)日：2024-12-19

申请号：US18821407

申请日：2024-08-30

Applicant: UNTETHER AI CORPORATION

Inventor： Joshua FENDER

IPC: G06F7/24 ,  G06F7/02

Abstract: A processing device having a sequence of sorting elements arranged in an array. Each of the sorting elements stores a previously retained value therein and receives an input value from a previous sorting element. Each sorting element applies retention logic to select one of the input value or the retained value to be passed to the next sorting element in the array. The value that is passed to the next sorting element can either be set to be the larger, or the smaller, of the input value and the previously retained value, as desired. Rows of processing elements in the array operate in parallel such that large data streams are sorted in parallel (with the data values moving down from one row of processing elements to the next row such that the largest, or the smallest, data values accumulating in the final row of processing elements).

公开(公告)号：US20240385844A1

公开(公告)日：2024-11-21

申请号：US18788433

申请日：2024-07-30

Applicant: UNTETHER AI CORPORATION

Inventor： William Martin SNELGROVE ,  Darrick WIEBE

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/02 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  G06F15/78 ,  G06N3/045 ,  G06N3/063

Abstract: An example device includes a plurality of computational memory banks. Each computational memory bank of the plurality of computational memory banks includes an array of memory units and a plurality of processing elements connected to the array of memory units. The device further includes a plurality of single instruction, multiple data (SIMD) controllers. Each SIMD controller of the plurality of SIMD controllers is contained within at least one computational memory bank of the plurality of computational memory banks. Each SIMD controller is to provide instructions to the at least one computational memory bank.

公开(公告)号：US11941405B2

公开(公告)日：2024-03-26

申请号：US18227092

申请日：2023-07-27

Applicant: UNTETHER AI CORPORATION

Inventor： William Martin Snelgrove ,  Darrick John Wiebe

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/02 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  G06F15/78 ,  G06N3/045 ,  G06N3/063

CPC classification number: G06F9/3887 ,  G06F9/3001 ,  G06F9/30101 ,  G06F12/0284 ,  G06F13/1668 ,  G06F13/287 ,  G06F13/4068 ,  G06F15/7821 ,  G06N3/045 ,  G06N3/063 ,  G06F2212/1028

Abstract: An example device includes a plurality of computational memory banks. Each computational memory bank of the plurality of computational memory banks includes an array of memory units and a plurality of processing elements connected to the array of memory units. The device further includes a plurality of single instruction, multiple data (SIMD) controllers. Each SIMD controller of the plurality of SIMD controllers is contained within at least one computational memory bank of the plurality of computational memory banks. Each SIMD controller is to provide instructions to the at least one computational memory bank.

公开(公告)号：US20200293316A1

公开(公告)日：2020-09-17

申请号：US16815535

申请日：2020-03-11

Applicant: UNTETHER AI CORPORATION

Inventor： Trevis CHANDLER ,  Pasquale LEONE ,  William Martin SNELGROVE ,  Darrick John WIEBE

IPC: G06F9/30 ,  G06F15/80

Abstract: A processing device includes an array of processing elements, each processing element including an arithmetic logic unit to perform an operation. The processing device further includes interconnections among the array of processing elements to provide direct communication among neighboring processing elements of the array of processing elements. A processing element of the array of processing elements may be connected to a first neighbor processing element that is immediately adjacent the processing element. The processing element may be further connected to a second neighbor processing element that is immediately adjacent the first neighbor processing element. A processing element of the array of processing elements may be connected to a neighbor processing element via an input selector to selectively take output of the neighbor processing element as input to the processing element. A computing device may include such processing devices in an arrangement of banks.

公开(公告)号：US12106068B2

公开(公告)日：2024-10-01

申请号：US17874454

申请日：2022-07-27

Applicant: UNTETHER AI CORPORATION

Inventor： Joshua Fender

IPC: G06F7/24 ,  G06F7/02

CPC classification number: G06F7/24 ,  G06F7/02

Abstract: A processing device having a sequence of sorting elements arranged in an array. Each of the sorting elements stores a previously retained value therein and receives an input value from a previous sorting element. Each sorting element applies retention logic to select one of the input value or the retained value to be passed to the next sorting element in the array. The value that is passed to the next sorting element can either be set to be the larger, or the smaller, of the input value and the previously retained value, as desired. Rows of processing elements in the array operate in parallel such that large data streams are sorted in parallel (with the data values moving down from one row of processing elements to the next row such that the largest, or the smallest, data values accumulating in the final row of processing elements).

公开(公告)号：US11955170B2

公开(公告)日：2024-04-09

申请号：US18235954

申请日：2023-08-21

Applicant: UNTETHER AI CORPORATION

Inventor： Katsuyuki Sato ,  William Martin Snelgrove ,  Saijagan Saijagan ,  Joseph Francis Rohlman

IPC: G11C11/418 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/412 ,  G11C11/419

Abstract: A static random-access memory is set forth comprising: a word line circuit for generating a word line signal on a word line; a plurality of six-transistor memory cells arranged between a first bitline, a second bitline and the word line for simultaneously selecting one of either all or a portion of the plurality of six-transistor memory cells for data reading or writing, and wherein each memory cell includes first and second n-channel transistors and a bitline precharge circuit for precharging the first bitline and second bitline to a voltage of Vdd/2 prior to the first and second n-channel transistors receiving the word line signal.

公开(公告)号：US11934482B2

公开(公告)日：2024-03-19

申请号：US18230139

申请日：2023-08-03

Applicant: UNTETHER AI CORPORATION

Inventor： William Martin Snelgrove

IPC: G06F17/16 ,  G06F7/53 ,  G06F7/544 ,  G06F7/575 ,  G06F9/30

CPC classification number: G06F17/16 ,  G06F7/5324 ,  G06F7/5443 ,  G06F7/575 ,  G06F9/30101

Abstract: A processing device includes a two-dimensional array of processing elements, each processing element including an arithmetic logic unit to perform an operation. The device further includes interconnections among the two-dimensional array of processing elements to provide direct communication among neighboring processing elements of the two-dimensional array of processing elements. A processing element of the two-dimensional array of processing elements is connected to a first neighbor processing element that is immediately adjacent the processing element in a first dimension of the two-dimensional array. The processing element is further connected to a second neighbor processing element that is immediately adjacent the processing element in a second dimension of the two-dimensional array.

公开(公告)号：US20240036818A1

公开(公告)日：2024-02-01

申请号：US17874454

申请日：2022-07-27

Applicant: UNTETHER AI CORPORATION

Inventor： Joshua FENDER

IPC: G06F7/24 ,  G06F7/02

CPC classification number: G06F7/24 ,  G06F7/02

Abstract: A processing device having a sequence of sorting elements arranged in an array. Each of the sorting elements stores a previously retained value therein and receives an input value from a previous sorting element. Each sorting element applies retention logic to select one of the input value or the retained value to be passed to the next sorting element in the array. The value that is passed to the next sorting element can either be set to be the larger, or the smaller, of the input value and the previously retained value, as desired. Rows of processing elements in the array operate in parallel such that large data streams are sorted in parallel (with the data values moving down from one row of processing elements to the next row such that the largest, or the smallest, data values accumulating in the final row of processing elements).

公开(公告)号：US20230376563A1

公开(公告)日：2023-11-23

申请号：US18230139

申请日：2023-08-03

Applicant: UNTETHER AI CORPORATION

Inventor： William Martin SNELGROVE

IPC: G06F17/16 ,  G06F7/575 ,  G06F9/30 ,  G06F7/544 ,  G06F7/53

CPC classification number: G06F17/16 ,  G06F7/575 ,  G06F9/30101 ,  G06F7/5443 ,  G06F7/5324

Abstract: A processing device includes a two-dimensional array of processing elements, each processing element including an arithmetic logic unit to perform an operation. The device further includes interconnections among the two-dimensional array of processing elements to provide direct communication among neighboring processing elements of the two-dimensional array of processing elements. A processing element of the two-dimensional array of processing elements is connected to a first neighbor processing element that is immediately adjacent the processing element in a first dimension of the two-dimensional array. The processing element is further connected to a second neighbor processing element that is immediately adjacent the processing element in a second dimension of the two-dimensional array.

公开(公告)号：US20230367739A1

公开(公告)日：2023-11-16

申请号：US18224146

申请日：2023-07-20

Applicant: UNTETHER AI CORPORATION

Inventor： William Martin SNELGROVE ,  Jonathan SCOBBIE

IPC: G06F15/80 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F15/8015 ,  G06F9/3887 ,  G06F9/3001 ,  G06F9/30047 ,  G06F1/32

Abstract: A computing device includes an array of processing elements mutually connected to perform single instruction multiple data (SIMD) operations, memory cells connected to each processing element to store data related to the SIMD operations, and a cache connected to each processing element to cache data related to the SIMD operations. Caches of adjacent processing elements are connected. The same or another computing device includes rows of mutually connected processing elements to share data. The computing device further includes a row arithmetic logic unit (ALU) at each row of processing elements. The row ALU of a respective row is configured to perform an operation with processing elements of the respective row.