-
公开(公告)号：US20200293316A1
公开(公告)日：2020-09-17
申请号：US16815535
申请日：2020-03-11
摘要： A processing device includes an array of processing elements, each processing element including an arithmetic logic unit to perform an operation. The processing device further includes interconnections among the array of processing elements to provide direct communication among neighboring processing elements of the array of processing elements. A processing element of the array of processing elements may be connected to a first neighbor processing element that is immediately adjacent the processing element. The processing element may be further connected to a second neighbor processing element that is immediately adjacent the first neighbor processing element. A processing element of the array of processing elements may be connected to a neighbor processing element via an input selector to selectively take output of the neighbor processing element as input to the processing element. A computing device may include such processing devices in an arrangement of banks.
-
公开(公告)号：US20240362456A1
公开(公告)日：2024-10-31
申请号：US18770518
申请日：2024-07-11
CPC分类号： G06N3/045 , G06F9/3887 , G06F13/4022 , G06N3/063 , Y02D10/00
摘要： A system and method for enhancing C*RAM, improving its performance for known applications such as video processing but also making it well suited to low-power implementation of neural nets. The required computing engine is decomposed into banks of enhanced C*RAM each having a SIMD controller, thus allowing operations at several scales simultaneously. Several configurations of suitable controllers are discussed, along with communication structures and enhanced processing elements.
-
公开(公告)号：US20230229450A1
公开(公告)日：2023-07-20
申请号：US18126574
申请日：2023-03-27
IPC分类号： G06F9/38 , G06F9/30 , G06F12/02 , G06F15/78 , G06F13/40 , G06F13/28 , G06N3/063 , G06F13/16 , G06N3/045
CPC分类号： G06F9/3887 , G06F9/3001 , G06F9/30101 , G06F12/0284 , G06F15/7821 , G06F13/4068 , G06F13/287 , G06N3/063 , G06F13/1668 , G06N3/045 , G06F2212/1028
摘要： An example device includes a plurality of computational memory banks. Each computational memory bank of the plurality of computational memory banks includes an array of memory units and a plurality of processing elements connected to the array of memory units. The device further includes a plurality of single instruction, multiple data (SIMD) controllers. Each SIMD controller of the plurality of SIMD controllers is contained within at least one computational memory bank of the plurality of computational memory banks. Each SIMD controller is to provide instructions to the at least one computational memory bank.
-
4.发明申请公开(公告)号：US20210271631A1
公开(公告)日：2021-09-02
申请号：US17187082
申请日：2021-02-26
摘要： A computing device includes an array of processing elements mutually connected to perform single instruction multiple data (SIMD) operations, memory cells connected to each processing element to store data related to the SIMD operations, and a cache connected to each processing element to cache data related to the SIMD operations. Caches of adjacent processing elements are connected. The same or another computing device includes rows of mutually connected processing elements to share data. The computing device further includes a row arithmetic logic unit (ALU) at each row of processing elements. The row ALU of a respective row is configured to perform an operation with processing elements of the respective row.
-
公开(公告)号：US20230376563A1
公开(公告)日：2023-11-23
申请号：US18230139
申请日：2023-08-03
CPC分类号： G06F17/16 , G06F7/575 , G06F9/30101 , G06F7/5443 , G06F7/5324
摘要： A processing device includes a two-dimensional array of processing elements, each processing element including an arithmetic logic unit to perform an operation. The device further includes interconnections among the two-dimensional array of processing elements to provide direct communication among neighboring processing elements of the two-dimensional array of processing elements. A processing element of the two-dimensional array of processing elements is connected to a first neighbor processing element that is immediately adjacent the processing element in a first dimension of the two-dimensional array. The processing element is further connected to a second neighbor processing element that is immediately adjacent the processing element in a second dimension of the two-dimensional array.
-
6.发明公开公开(公告)号：US20230367739A1
公开(公告)日：2023-11-16
申请号：US18224146
申请日：2023-07-20
CPC分类号： G06F15/8015 , G06F9/3887 , G06F9/3001 , G06F9/30047 , G06F1/32
摘要： A computing device includes an array of processing elements mutually connected to perform single instruction multiple data (SIMD) operations, memory cells connected to each processing element to store data related to the SIMD operations, and a cache connected to each processing element to cache data related to the SIMD operations. Caches of adjacent processing elements are connected. The same or another computing device includes rows of mutually connected processing elements to share data. The computing device further includes a row arithmetic logic unit (ALU) at each row of processing elements. The row ALU of a respective row is configured to perform an operation with processing elements of the respective row.
-
公开(公告)号：US20230395142A1
公开(公告)日：2023-12-07
申请号：US18251251
申请日：2022-06-21
IPC分类号： G11C11/419 , G11C5/14 , G11C7/12 , G11C7/18 , G11C7/10
CPC分类号： G11C11/419 , G11C5/14 , G11C7/1048 , G11C7/18 , G11C7/12
摘要： A low-power static random access memory (SRAM) is set forth which includes a cache memory function without requiring a special bit cell, and which realizes robust read and write operation without any write assist circuit at 16 nm or below FinFET technology. The SRAM comprises a half-Vdd precharge 6T SRAM cell array for robust operation at low supply voltage at 16 nm or below, and with cacheable dynamic flip-flop based differential amplifier referred to as a main amplifier (MA). Prior art 6T SRAM cell arrays use Vdd or Vdd-Vth precharge schemes, and have separate read and write amplifiers. The SRAM set forth uses one main amplifier only, which is connected to the bit line (BL) through a transmission gate. The main amplifiers functions as a read amplifier, write amplifier, and a cache memory.
-
公开(公告)号：US20230069360A1
公开(公告)日：2023-03-02
申请号：US17984722
申请日：2022-11-10
摘要： A system and method for enhancing C*RAM, improving its performance for known applications such as video processing but also making it well suited to low-power implementation of neural nets. The required computing engine is decomposed into banks of enhanced C*RAM each having a SIMD controller, thus allowing operations at several scales simultaneously. Several configurations of suitable controllers are discussed, along with communication structures and enhanced processing elements.
-
9.发明申请公开(公告)号：US20230004522A1
公开(公告)日：2023-01-05
申请号：US17942816
申请日：2022-09-12
摘要： A computing device includes an array of processing elements mutually connected to perform single instruction multiple data (SIMD) operations, memory cells connected to each processing element to store data related to the SIMD operations, and a cache connected to each processing element to cache data related to the SIMD operations. Caches of adjacent processing elements are connected. The same or another computing device includes rows of mutually connected processing elements to share data. The computing device further includes a row arithmetic logic unit (ALU) at each row of processing elements. The row ALU of a respective row is configured to perform an operation with processing elements of the respective row.
-
公开(公告)号：US20220171829A1
公开(公告)日：2022-06-02
申请号：US17675729
申请日：2022-02-18
摘要： A processing device includes a two-dimensional array of processing elements, each processing element including an arithmetic logic unit to perform an operation. The device further includes interconnections among the two-dimensional array of processing elements to provide direct communication among neighboring processing elements of the two-dimensional array of processing elements. A processing element of the two-dimensional array of processing elements is connected to a first neighbor processing element that is immediately adjacent the processing element in a first dimension of the two-dimensional array. The processing element is further connected to a second neighbor processing element that is immediately adjacent the processing element in a second dimension of the two-dimensional array.
-
-
-
-
-
-
-
-
-
搜索结果
17 条记录 (耗时 0.016 秒)
