公开(公告)号：US20230367739A1

公开(公告)日：2023-11-16

申请号：US18224146

申请日：2023-07-20

Applicant: UNTETHER AI CORPORATION

Inventor： William Martin SNELGROVE ,  Jonathan SCOBBIE

IPC: G06F15/80 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F15/8015 ,  G06F9/3887 ,  G06F9/3001 ,  G06F9/30047 ,  G06F1/32

Abstract: A computing device includes an array of processing elements mutually connected to perform single instruction multiple data (SIMD) operations, memory cells connected to each processing element to store data related to the SIMD operations, and a cache connected to each processing element to cache data related to the SIMD operations. Caches of adjacent processing elements are connected. The same or another computing device includes rows of mutually connected processing elements to share data. The computing device further includes a row arithmetic logic unit (ALU) at each row of processing elements. The row ALU of a respective row is configured to perform an operation with processing elements of the respective row.

公开(公告)号：US20230004522A1

公开(公告)日：2023-01-05

申请号：US17942816

申请日：2022-09-12

Applicant: UNTETHER AI CORPORATION

Inventor： William Martin SNELGROVE ,  Jonathan SCOBBIE

IPC: G06F15/80 ,  G06F9/38 ,  G06F9/30

Abstract: A computing device includes an array of processing elements mutually connected to perform single instruction multiple data (SIMD) operations, memory cells connected to each processing element to store data related to the SIMD operations, and a cache connected to each processing element to cache data related to the SIMD operations. Caches of adjacent processing elements are connected. The same or another computing device includes rows of mutually connected processing elements to share data. The computing device further includes a row arithmetic logic unit (ALU) at each row of processing elements. The row ALU of a respective row is configured to perform an operation with processing elements of the respective row.

公开(公告)号：US20250036592A1

公开(公告)日：2025-01-30

申请号：US18919520

申请日：2024-10-18

Applicant: UNTETHER AI CORPORATION

Inventor： William Martin SNELGROVE ,  Jonathan SCOBBIE

IPC: G06F15/80 ,  G06F1/32 ,  G06F9/30 ,  G06F9/38 ,  G06N3/04 ,  G06N3/08

Abstract: A computing device includes an array of processing elements mutually connected to perform single instruction multiple data (SIMD) operations, memory cells connected to each processing element to store data related to the SIMD operations, and a cache connected to each processing element to cache data related to the SIMD operations. Caches of adjacent processing elements are connected. The same or another computing device includes rows of mutually connected processing elements to share data. The computing device further includes a row arithmetic logic unit (ALU) at each row of processing elements. The row ALU of a respective row is configured to perform an operation with processing elements of the respective row.