公开(公告)号：US11955170B2

公开(公告)日：2024-04-09

申请号：US18235954

申请日：2023-08-21

Applicant: UNTETHER AI CORPORATION

Inventor： Katsuyuki Sato ,  William Martin Snelgrove ,  Saijagan Saijagan ,  Joseph Francis Rohlman

IPC: G11C11/418 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/412 ,  G11C11/419

Abstract: A static random-access memory is set forth comprising: a word line circuit for generating a word line signal on a word line; a plurality of six-transistor memory cells arranged between a first bitline, a second bitline and the word line for simultaneously selecting one of either all or a portion of the plurality of six-transistor memory cells for data reading or writing, and wherein each memory cell includes first and second n-channel transistors and a bitline precharge circuit for precharging the first bitline and second bitline to a voltage of Vdd/2 prior to the first and second n-channel transistors receiving the word line signal.

公开(公告)号：US11990181B2

公开(公告)日：2024-05-21

申请号：US18251251

申请日：2022-06-21

Applicant: UNTETHER AI CORPORATION

Inventor： Katsuyuki Sato ,  William Martin Snelgrove ,  Saijagan Saijagan

IPC: G11C11/419 ,  G11C5/14 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/18

Abstract: A low-power static random access memory (SRAM) is set forth which includes a cache memory function without requiring a special bit cell, and which realizes robust read and write operation without any write assist circuit at 16 nm or below FinFET technology. The SRAM comprises a half-Vdd precharge 6T SRAM cell array for robust operation at low supply voltage at 16 nm or below, and with cacheable dynamic flip-flop based differential amplifier referred to as a main amplifier (MA). Prior art 6T SRAM cell arrays use Vdd or Vdd-Vth precharge schemes, and have separate read and write amplifiers. The SRAM set forth uses one main amplifier only, which is connected to the bit line (BL) through a transmission gate. The main amplifiers functions as a read amplifier, write amplifier, and a cache memory.

公开(公告)号：US12237008B2

公开(公告)日：2025-02-25

申请号：US18000694

申请日：2022-06-21

Applicant: UNTETHER AI CORPORATION

Inventor： Katsuyuki Sato ,  William Martin Snelgrove ,  Saijagan Saijagan ,  Joseph Francis Rohlman

IPC: G11C11/419 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/412 ,  G11C11/418

Abstract: A static random-access memory is set forth comprising: a word line circuit for generating a word line signal on a word line; a plurality of six-transistor memory cells arranged between a first bitline, a second bitline and the word line for simultaneously selecting one of either all or a portion of the plurality of six-transistor memory cells for data reading or writing, and wherein each memory cell includes first and second n-channel transistors and a bitline precharge circuit for precharging the first bitline and second bitline to a voltage of Vdd/2 prior to the first and second n-channel transistors receiving the word line signal.