公开(公告)号：US20180114749A1

公开(公告)日：2018-04-26

申请号：US15788753

申请日：2017-10-19

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Antonio Bambalan Dimaano, JR. ,  Roel Adeva ROBLES

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/4867 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32106 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Device and method of forming the device are disclosed. A device includes a buildup package substrate with top and bottom surfaces and a plurality of interlevel dielectric (ILD) layers with interconnect structures printed layer by layer and includes a die region and a non-die region on the top surface. A semiconductor die is disposed in the die and non-die regions of the package substrate and is electrically connected to the plurality of interconnect structures via a plurality of wire bonds. A plurality of conductive elements are disposed on the bottom surface of the package substrate and a dielectric layer encapsulates the semiconductor die, the wire bonds and the top surface of the buildup package substrate.