公开(公告)号：US11257807B2

公开(公告)日：2022-02-22

申请号：US17111220

申请日：2020-12-03

Applicant: United Microelectronics Corp.

Inventor： Ting-Yao Lin ,  Chun Chiang ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/74

Abstract: A semiconductor device of electrostatic discharge (ESD) protection is provided, including a deep N-type region, disposed in a substrate; a deep P-type region, disposed in the substrate; a first P-type well, disposed in the deep N-type region; a first N-type well, abutting to the first P-type well, disposed in the deep N-type region. Further, a second P-type well abutting to the first N-type well is disposed in the deep P-type region. A second N-type well abutting to the second P-type well is disposed in the deep P-type region. A side N-type well is disposed in the deep N-type region at an outer side of the first P-type well. A side P-type well is disposed in the deep P-type region at an outer side of the second N-type well.

公开(公告)号：US10978442B2

公开(公告)日：2021-04-13

申请号：US16446599

申请日：2019-06-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ying-Wei Tseng ,  Chun Chiang ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H01L27/02

Abstract: An electrostatic discharge (ESD) protection device and a method thereof are presented. A well is disposed in a substrate. A gate is disposed on the well. A source region and a drain region are located in the well and at two opposite sides of the gate respectively. A first doped region is located in the drain region, wherein the first doped region is electrically connected to the drain region. A second doped region is located in the source region, wherein the second doped region is electrically connected to the source region. A third doped region is located in the well and at a side of the drain region opposite to the gate. A fourth doped region is located in the well and at a side of the source region opposite to the gate, wherein the fourth doped region is electrically connected to the third doped region.

公开(公告)号：US10903205B2

公开(公告)日：2021-01-26

申请号：US16394967

申请日：2019-04-25

Applicant: United Microelectronics Corp.

Inventor： Ting-Yao Lin ,  Chun Chiang ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/66

Abstract: A semiconductor device of ESD protection includes a first P-type well in a substrate to receive a protected terminal and a first N-type well abutting the first P-type well in the substrate. A second P-type well abutting the first N-type well is in the substrate. A second N-type well abutting the second P-type well is in the substrate. A detective circuit device is formed on a surface of the substrate, having an input terminal to receive the protected terminal and an output terminal to provide a trigger voltage to the first N-type well. A first route structure is in the substrate, on a sidewall and a bottom of the first P-type well to connect to a bottom of the first N-type well. A second route structure is in the substrate, on sidewall and bottom of the second N-type well, to connect to a bottom of the second P-type well.

公开(公告)号：US10522530B2

公开(公告)日：2019-12-31

申请号：US15927107

申请日：2018-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun Chiang ,  Ying-Wei Tseng ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H01L23/552 ,  H01L27/02 ,  H01L23/60 ,  G01R31/00 ,  G01R31/28 ,  H01L23/10

Abstract: An electrostatic discharge (ESD) shielding semiconductor device and an ESD testing method thereof, the ESD shielding semiconductor device includes an integrated circuit, a seal ring and a conductive layer. The integrated circuit is disposed on a die, and the integrated circuit has a first region and a second region. The seal ring is disposed on the die to surround the integrated circuit. The conductive layer at least covers the first region, and which is electrically connected to the seal ring.

公开(公告)号：US20210091069A1

公开(公告)日：2021-03-25

申请号：US17111220

申请日：2020-12-03

Applicant: United Microelectronics Corp.

Inventor： Ting-Yao Lin ,  Chun Chiang ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/74

Abstract: A semiconductor device of electrostatic discharge (ESD) protection is provided, including a deep N-type region, disposed in a substrate; a deep P-type region, disposed in the substrate; a first P-type well, disposed in the deep N-type region; a first N-type well, abutting to the first P-type well, disposed in the deep N-type region. Further, a second P-type well abutting to the first N-type well is disposed in the deep P-type region. A second N-type well abutting to the second P-type well is disposed in the deep P-type region. A side N-type well is disposed in the deep N-type region at an outer side of the first P-type well. A side P-type well is disposed in the deep P-type region at an outer side of the second N-type well.

公开(公告)号：US20200343238A1

公开(公告)日：2020-10-29

申请号：US16394967

申请日：2019-04-25

Applicant: United Microelectronics Corp.

Inventor： Ting-Yao Lin ,  Chun Chiang ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/66

Abstract: A semiconductor device of ESD protection includes a first P-type well in a substrate to receive a protected terminal and a first N-type well abutting the first P-type well in the substrate. A second P-type well abutting the first N-type well is in the substrate. A second N-type well abutting the second P-type well is in the substrate. A detective circuit device is formed on a surface of the substrate, having an input terminal to receive the protected terminal and an output terminal to provide a trigger voltage to the first N-type well. A first route structure is in the substrate, on a sidewall and a bottom of the first P-type well to connect to a bottom of the first N-type well. A second route structure is in the substrate, on sidewall and bottom of the second N-type well, to connect to a bottom of the second P-type well.

公开(公告)号：US11004840B2

公开(公告)日：2021-05-11

申请号：US16200662

申请日：2018-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Che Yen ,  Tien-Hao Tang ,  Chun Chiang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H02H9/04

Abstract: A silicon controlled rectifier includes a substrate, an N-type well, a P-type well, a gate structure, a first N-type doped region, a second N-type doped region, a first P-type doped region, a second P-type doped region, a first STI, and a second STI. The N-type well and the P-type well are disposed in the substrate. The gate structure is disposed on the P-type well. The first N-type doped region is disposed in the N-type well at one side of the gate structure. The second N-type doped region is disposed in the P-type well at another side of the gate structure. The first P-type doped region is disposed in the N-type well. The second P-type doped region is disposed in the P-type well. The first STI is between the first N-type and first P-type doped regions. The second STI is between the second N-type and second P-type doped regions.

公开(公告)号：US20200381415A1

公开(公告)日：2020-12-03

申请号：US16446599

申请日：2019-06-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ying-Wei Tseng ,  Chun Chiang ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H01L27/02

Abstract: An electrostatic discharge (ESD) protection device and a method thereof are presented. A well is disposed in a substrate. A gate is disposed on the well. A source region and a drain region are located in the well and at two opposite sides of the gate respectively. A first doped region is located in the drain region, wherein the first doped region is electrically connected to the drain region. A second doped region is located in the source region, wherein the second doped region is electrically connected to the source region. A third doped region is located in the well and at a side of the drain region opposite to the gate. A fourth doped region is located in the well and at a side of the source region opposite to the gate, wherein the fourth doped region is electrically connected to the third doped region.

公开(公告)号：US20190273077A1

公开(公告)日：2019-09-05

申请号：US15927107

申请日：2018-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun Chiang ,  Ying-Wei Tseng ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L23/60 ,  H01L23/10 ,  G01R31/28 ,  G01R31/00

Abstract: An electrostatic discharge (ESD) shielding semiconductor device and an ESD testing method thereof, the ESD shielding semiconductor device includes an integrated circuit, a seal ring and a conductive layer. The integrated circuit is disposed on a die, and the integrated circuit has a first region and a second region. The seal ring is disposed on the die to surround the integrated circuit. The conductive layer at least covers the first region, and which is electrically connected to the seal ring.