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公开(公告)号：US20240332421A1
公开(公告)日：2024-10-03
申请号：US18227979
申请日：2023-07-31
发明人： Po-Yu Yang , Chun-Hsien Lin
IPC分类号： H01L29/78 , H01L29/40 , H01L29/423 , H01L29/51 , H01L29/66
CPC分类号： H01L29/7851 , H01L29/401 , H01L29/42364 , H01L29/513 , H01L29/66795
摘要： A semiconductor device includes a first fin structure, an insulating structure, a first groove and a gate structure. The first fin structure is extended along a first direction on a substrate. The insulating structure surrounds the first fin structure. The first groove is extended along the first direction and disposed between the first fin structure and the insulating structure. The first groove exposes a first portion of the substrate. The gate structure is extended along a second direction on the first fin structure. At least a portion of the gate structure is disposed in the first groove. The gate structure includes a gate dielectric layer disposed on the first fin structure and the first portion of the substrate.
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公开(公告)号：US20240321993A1
公开(公告)日：2024-09-26
申请号：US18679459
申请日：2024-05-31
发明人： Po-Kuang Hsieh , Shih-Hung Tsai , Ching-Wen Hung , Chun-Hsien Lin
IPC分类号： H01L29/423 , H01L29/06 , H01L29/16 , H01L29/45 , H01L29/66 , H01L29/786
CPC分类号： H01L29/42392 , H01L29/0673 , H01L29/1606 , H01L29/45 , H01L29/66045 , H01L29/78696
摘要： A nanowire transistor includes a channel structure on a substrate, a gate structure on and around the channel structure, a source/drain structure adjacent to two sides of the gate structure, and a contact plug connected to the source/drain structure. Preferably, the source/drain structure includes graphene and the contact plug further includes a silicide layer on the source/drain structure, a graphene layer on the silicide layer, and a barrier layer on the graphene layer.
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公开(公告)号：US20240243124A1
公开(公告)日：2024-07-18
申请号：US18110353
申请日：2023-02-15
发明人： Chih-Wei Yang , Shih-Min Lu , Chi-Sheng Tseng , Yao-Jhan Wang , Chun-Hsien Lin
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L27/088 , H01L21/823456
摘要： A method for fabricating a semiconductor device includes the steps of first forming a first gate structure on a substrate and then forming a first epitaxial layer adjacent to the first gate structure. Preferably, a top surface of the first epitaxial layer includes a first curve, a second curve, and a third curve connecting the first curve and the second curve, in which the first curve and the second curve include curves concave downward while the third curve includes a curve concave upward.
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公开(公告)号：US20240006468A1
公开(公告)日：2024-01-04
申请号：US17876467
申请日：2022-07-28
发明人： Kuo-Hsing Lee , Chun-Hsien Lin , Chih-Wei Yang
摘要： A method for fabricating a resistor structure includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, patterning the p-type semiconductor layer, trimming the barrier layer along a first direction, and then forming an electrode on the barrier layer along a second direction.
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公开(公告)号：US20230403942A1
公开(公告)日：2023-12-14
申请号：US18239119
申请日：2023-08-28
发明人： Chia-Wei Liu , Jia-Feng Fang , Chun-Hsien Lin
摘要： A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.
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公开(公告)号：US20230386939A1
公开(公告)日：2023-11-30
申请号：US18233331
申请日：2023-08-14
发明人： Fu-Jung Chuang , Po-Jen Chuang , Yu-Ren Wang , Chi-Mao Hsu , Chia-Ming Kuo , Guan-Wei Huang , Chun-Hsien Lin
IPC分类号： H01L21/8238 , H01L27/092 , H01L21/762
CPC分类号： H01L21/823878 , H01L27/0924 , H01L21/76224 , H01L21/823821
摘要： A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the first fin-shaped structure into a first portion and a second portion, and more than two gate structures on the SDB structure. Preferably, the more than two gate structures include a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure disposed on the SDB structure.
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公开(公告)号：US20230380148A1
公开(公告)日：2023-11-23
申请号：US17844076
申请日：2022-06-20
发明人： Kuo-Hsing Lee , Chun-Hsien Lin , Chih-Kai Kang , Ting-Hsiang Huang , Chien-Liang Wu , Sheng-Yuan Hsueh , Chi-Horn Pai
IPC分类号： H01L27/112
CPC分类号： H01L27/11206
摘要： A method for fabricating a semiconductor device includes the steps of first providing a substrate having an one time programmable (OTP) device region, forming a shallow trench isolation (STI) in the substrate, forming a first doped region adjacent to the STI, removing part of the STI, and then forming a first gate structure on the substrate and the STI. Preferably, the first gate structure includes a high-k dielectric layer on the substrate and a gate electrode on the high-k dielectric layer, in which the high-k dielectric layer comprises a first L-shape.
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公开(公告)号：US11765891B2
公开(公告)日：2023-09-19
申请号：US17391067
申请日：2021-08-02
发明人： Kuo-Hsing Lee , Sheng-Yuan Hsueh , Chun-Hsien Lin , Yung-Chen Chiu , Chien-Liang Wu , Te-Wei Yeh
摘要： A one-time programmable (OTP) memory cell includes a substrate having a first conductivity type and having an active area surrounded by an isolation region, a transistor disposed on the active area, and a capacitor disposed on the active area and electrically coupled to the transistor. The capacitor comprises a diffusion region of a second conductivity type in the substrate, a metallic film in direct contact with the active area, a capacitor dielectric layer on the metallic film, and a metal gate surrounded by the capacitor dielectric layer. The diffusion region and the metallic film constitute a capacitor bottom plate.
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公开(公告)号：US20230100606A1
公开(公告)日：2023-03-30
申请号：US18075396
申请日：2022-12-05
发明人： Chun-Hsien Lin
摘要： A method for fabricating a semiconductor device includes the steps of: forming a fin-shaped structure on a substrate, forming a gate material layer on the fin-shaped structure, performing an etching process to pattern the gate material layer for forming a gate structure and a silicon residue, performing an ashing process on the silicon residue, and then performing a cleaning process to transform the silicon residue into a polymer stop layer on a top surface and sidewalls of the fin-shaped structure.
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公开(公告)号：US20220392905A1
公开(公告)日：2022-12-08
申请号：US17363015
申请日：2021-06-30
发明人： Kuo-Hsing Lee , Chun-Hsien Lin , Chih-Wei Yang , Chang-Chien Wong , Te-Wei Yeh , Sheng-Yuan Hsueh
IPC分类号： H01L27/112
摘要： A method for fabricating an one time programmable (OTP) device includes the steps of: forming a first gate structure and a second gate structure extending along a first direction on a substrate; forming a diffusion region adjacent to two sides of the first gate structure and the second gate structure; forming a silicide layer adjacent to the first gate structure; and patterning the first gate structure for forming a third gate structure and a fourth gate structure.
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