公开(公告)号：US12262645B2

公开(公告)日：2025-03-25

申请号：US18224066

申请日：2023-07-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, an inter-metal dielectric (IMD) layer on the substrate, a MTJ in the IMD layer on the MTJ region, a first metal interconnection in the IMD layer on the logic region, and protrusions adjacent to two sides of the first metal interconnection. Preferably, the MTJ further includes a bottom electrode, a fixed layer, a barrier layer, a free layer, and a top electrode.

公开(公告)号：US20250072294A1

公开(公告)日：2025-02-27

申请号：US18946936

申请日：2024-11-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Wei Liu ,  Jia-Feng Fang ,  Chun-Hsien Lin

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.

公开(公告)号：US20250048659A1

公开(公告)日：2025-02-06

申请号：US18367468

申请日：2023-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Yih Chen ,  Kuo-Hsing Lee ,  Chun-Hsien Lin

IPC: H01L29/66 ,  H01L27/06 ,  H01L29/78 ,  H01L29/94

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising a non-metal-oxide semiconductor capacitor (non-MOSCAP) region and a MOSCAP region, forming a first fin-shaped structure on the MOSCAP region, forming a doped layer on the substrate of the non-MOSCAP region and the first fin-shaped structure on the MOSCAP region, removing the doped layer on the non-MOSCAP region, and then performing an anneal process to drive dopants from the doped layer into the first fin-shaped structure.

公开(公告)号：US12178136B2

公开(公告)日：2024-12-24

申请号：US18239119

申请日：2023-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Wei Liu ,  Jia-Feng Fang ,  Chun-Hsien Lin

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.

公开(公告)号：US20240332421A1

公开(公告)日：2024-10-03

申请号：US18227979

申请日：2023-07-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Chun-Hsien Lin

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/66795

Abstract: A semiconductor device includes a first fin structure, an insulating structure, a first groove and a gate structure. The first fin structure is extended along a first direction on a substrate. The insulating structure surrounds the first fin structure. The first groove is extended along the first direction and disposed between the first fin structure and the insulating structure. The first groove exposes a first portion of the substrate. The gate structure is extended along a second direction on the first fin structure. At least a portion of the gate structure is disposed in the first groove. The gate structure includes a gate dielectric layer disposed on the first fin structure and the first portion of the substrate.

公开(公告)号：US20240321993A1

公开(公告)日：2024-09-26

申请号：US18679459

申请日：2024-05-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai ,  Ching-Wen Hung ,  Chun-Hsien Lin

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/16 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/1606 ,  H01L29/45 ,  H01L29/66045 ,  H01L29/78696

Abstract: A nanowire transistor includes a channel structure on a substrate, a gate structure on and around the channel structure, a source/drain structure adjacent to two sides of the gate structure, and a contact plug connected to the source/drain structure. Preferably, the source/drain structure includes graphene and the contact plug further includes a silicide layer on the source/drain structure, a graphene layer on the silicide layer, and a barrier layer on the graphene layer.

公开(公告)号：US20240243124A1

公开(公告)日：2024-07-18

申请号：US18110353

申请日：2023-02-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Shih-Min Lu ,  Chi-Sheng Tseng ,  Yao-Jhan Wang ,  Chun-Hsien Lin

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823456

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first gate structure on a substrate and then forming a first epitaxial layer adjacent to the first gate structure. Preferably, a top surface of the first epitaxial layer includes a first curve, a second curve, and a third curve connecting the first curve and the second curve, in which the first curve and the second curve include curves concave downward while the third curve includes a curve concave upward.

公开(公告)号：US20240006468A1

公开(公告)日：2024-01-04

申请号：US17876467

申请日：2022-07-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Chun-Hsien Lin ,  Chih-Wei Yang

IPC: H01L49/02 ,  H01C17/22

CPC classification number: H01L28/24 ,  H01C17/22

Abstract: A method for fabricating a resistor structure includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, patterning the p-type semiconductor layer, trimming the barrier layer along a first direction, and then forming an electrode on the barrier layer along a second direction.

公开(公告)号：US20230403942A1

公开(公告)日：2023-12-14

申请号：US18239119

申请日：2023-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Wei Liu ,  Jia-Feng Fang ,  Chun-Hsien Lin

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/22 ,  H10N50/80 ,  H10N50/85

Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.

公开(公告)号：US20230386939A1

公开(公告)日：2023-11-30

申请号：US18233331

申请日：2023-08-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Chi-Mao Hsu ,  Chia-Ming Kuo ,  Guan-Wei Huang ,  Chun-Hsien Lin

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/762

CPC classification number: H01L21/823878 ,  H01L27/0924 ,  H01L21/76224 ,  H01L21/823821

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the first fin-shaped structure into a first portion and a second portion, and more than two gate structures on the SDB structure. Preferably, the more than two gate structures include a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure disposed on the SDB structure.