公开(公告)号：US20200266267A1

公开(公告)日：2020-08-20

申请号：US16358556

申请日：2019-03-19

Applicant: United Microelectronics Corp.

Inventor： HSIANG-HUA HSU ,  Liang-An Huang ,  Sheng-Chen Chung ,  Chen-An Kuo ,  Chiu-Te Lee ,  Chih-Chung Wang ,  Kuang-Hsiu Chen ,  Ke-Feng Lin ,  Yan-Huei Li ,  Kai-Ting Hu

IPC: H01L29/06 ,  H01L29/778 ,  H01L29/66 ,  H01L21/265

Abstract: A metal-oxide-semiconductor (MOS) transistor includes a substrate. The substrate has a plurality of trenches extending along a first direction and located on a top portion of the substrate. A gate structure line is located on the substrate and extends along a second direction intersecting with the first direction and crossing over the trenches. A first doped line is located in the substrate, located at a first side of the gate structure line, and crosses over the trenches. A second doped line is located in the substrate, located at a second side of the gate structure line, and crosses over the trenches.

公开(公告)号：US09437471B2

公开(公告)日：2016-09-06

申请号：US14572788

申请日：2014-12-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang-An Huang

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76229 ,  H01L29/0653

Abstract: A method of manufacturing shallow trench isolations is provided in the present invention, which includes the steps of providing a substrate, performing a zero etch to form preliminary trenches in the substrate, performing a STI etch to the preliminary trenches to form final trenches, where the final trenches are deeper and steeper than the preliminary trenches, and filling up the final trenches with insulating material to form shallow trench isolations.

Abstract translation: 在本发明中提供了制造浅沟槽隔离的方法，其包括提供衬底，执行零蚀刻以在衬底中形成初步沟槽的步骤，对初步沟槽执行STI蚀刻以形成最终沟槽，其中 最后的沟槽比初始沟槽更深，更陡，并用绝缘材料填充最终的沟槽以形成浅沟槽隔离。

公开(公告)号：US20160181146A1

公开(公告)日：2016-06-23

申请号：US14572788

申请日：2014-12-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang-An Huang

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76229 ,  H01L29/0653

Abstract: A method of manufacturing shallow trench isolations is provided in the present invention, which includes the steps of providing a substrate, performing a zero etch to form preliminary trenches in the substrate, performing a STI etch to the preliminary trenches to form final trenches, where the final trenches are deeper and steeper than the preliminary trenches, and filling up the final trenches with insulating material to form shallow trench isolations.

Abstract translation: 在本发明中提供了制造浅沟槽隔离的方法，其包括提供衬底，执行零蚀刻以在衬底中形成初步沟槽的步骤，对初步沟槽执行STI蚀刻以形成最终沟槽，其中 最后的沟槽比初始沟槽更深，更陡，并用绝缘材料填充最终的沟槽以形成浅沟槽隔离。

公开(公告)号：US20240234572A1

公开(公告)日：2024-07-11

申请号：US18108019

申请日：2023-02-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang-An Huang ,  Ming-Hua Tsai ,  Wen-Fang Lee ,  Chin-Chia Kuo ,  Jung Han ,  Chun-Lin Chen ,  Ching-Chung Yang ,  Nien-Chung Li

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7835 ,  H01L29/1033 ,  H01L29/42364 ,  H01L29/7801

Abstract: An extended drain metal oxide semiconductor transistor includes a substrate. A gate is disposed on the substrate. A source doped region is disposed in the substrate at one side of the gate. A drain doped region is disposed in the substrate at another side of the gate. A thin gate dielectric layer is disposed under the gate. A thick gate dielectric layer is disposed under the gate. The thick gate dielectric layer extends from the bottom of the gate to contact the drain doped region. A second conductive type first well is disposed in the substrate and surrounds the source doped region and the drain doped region. A deep well is disposed within the substrate and surrounds the second conductive type first well.

公开(公告)号：US11195905B2

公开(公告)日：2021-12-07

申请号：US16358556

申请日：2019-03-19

Applicant: United Microelectronics Corp.

Inventor： Hsiang-Hua Hsu ,  Liang-An Huang ,  Sheng-Chen Chung ,  Chen-An Kuo ,  Chiu-Te Lee ,  Chih-Chung Wang ,  Kuang-Hsiu Chen ,  Ke-Feng Lin ,  Yan-Huei Li ,  Kai-Ting Hu

IPC: H01L29/06 ,  H01L21/265 ,  H01L29/66 ,  H01L29/778

Abstract: A metal-oxide-semiconductor (MOS) transistor includes a substrate. The substrate has a plurality of trenches extending along a first direction and located on a top portion of the substrate. A gate structure line is located on the substrate and extends along a second direction intersecting with the first direction and crossing over the trenches. A first doped line is located in the substrate, located at a first side of the gate structure line, and crosses over the trenches. A second doped line is located in the substrate, located at a second side of the gate structure line, and crosses over the trenches.