公开(公告)号：US20250056868A1

公开(公告)日：2025-02-13

申请号：US18460605

申请日：2023-09-04

Applicant: United Microelectronics Corp.

Inventor： Ming-Hua Tsai ,  Wei Hsuan Chang ,  Chin-Chia Kuo

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A method of fabricating a semiconductor device is provided. Recesses are formed in a substrate. A first gate dielectric material is formed on the substrate and filled in the recesses. The first gate dielectric material on the substrate between the recesses is at least partially removed to form a trench. A second gate dielectric material is formed in the trench. A gate conductive layer is formed on the second gate dielectric material. Spacers are formed on sidewalls of the gate conductive layer. A portion of the first gate dielectric material is removed. The remaining first gate dielectric material and the second gate dielectric layer form a gate dielectric layer. The gate dielectric layer includes a body part and a first hump part at a first edge of the body part. The first hump part is thicker than the body part. Doped regions are formed in the substrate beside the spacers.

公开(公告)号：US11569380B2

公开(公告)日：2023-01-31

申请号：US17366053

申请日：2021-07-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsuan Chang ,  Ming-Hua Tsai ,  Chin-Chia Kuo

IPC: H01L29/78 ,  H01L29/45

Abstract: A semiconductor structure is provided, and the semiconductor structure includes a substrate, and an active area is defined thereon, a gate structure spanning the active area, wherein the overlapping range of the gate structure and the active area is defined as an overlapping region, and the overlapping region includes four corners, and at least one salicide block covering the four corners of the overlapping region.

公开(公告)号：US11545447B2

公开(公告)日：2023-01-03

申请号：US17394394

申请日：2021-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsuan Chang ,  Ming-Hua Tsai ,  Chin-Chia Kuo

IPC: H01L23/00 ,  H01L21/762 ,  H01L27/06 ,  H01L49/02 ,  H01L23/522 ,  H01L27/08 ,  H01L21/3105

Abstract: A semiconductor device includes a substrate, a first isolation structure, a second isolation structure and a dummy pattern. The substrate includes a first part surrounding a second part at a top view. The first isolation structure is disposed between the first part and the second part, to isolate the first part from the second part. The second isolation structure is disposed at at least one corner of the first part. The dummy pattern is disposed on the second isolation structure. The present invention also provides a method of forming said semiconductor device.

公开(公告)号：US20210366843A1

公开(公告)日：2021-11-25

申请号：US17394394

申请日：2021-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsuan Chang ,  Ming-Hua Tsai ,  Chin-Chia Kuo

IPC: H01L23/00 ,  H01L49/02 ,  H01L23/522 ,  H01L21/762 ,  H01L27/06 ,  H01L27/08

Abstract: A semiconductor device includes a substrate, a first isolation structure, a second isolation structure and a dummy pattern. The substrate includes a first part surrounding a second part at a top view. The first isolation structure is disposed between the first part and the second part, to isolate the first part from the second part. The second isolation structure is disposed at at least one corner of the first part. The dummy pattern is disposed on the second isolation structure. The present invention also provides a method of forming said semiconductor device.

公开(公告)号：US10141398B1

公开(公告)日：2018-11-27

申请号：US15844942

申请日：2017-12-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Tsai ,  Jung Han ,  Chin-Chia Kuo ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L27/118 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L21/28 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49

Abstract: A semiconductor structure includes a HV NMOS structure. The HV NMOS structure includes a source region, a drain region, a channel region, a gate dielectric, and a gate electrode. The source region and the drain region are separated from each other. The channel region is disposed between the source region and the drain region. The channel region has a channel direction from the source region toward the drain region. The gate dielectric is disposed on the channel region and on portions of the source region and the drain region. The gate electrode is disposed on the gate dielectric. The gate electrode includes a first portion of n-type doping and two second portions of p-type doping. The two second portions are disposed at two sides of the first portion. The two second portions have an extending direction perpendicular to the channel direction.

公开(公告)号：US20240234572A1

公开(公告)日：2024-07-11

申请号：US18108019

申请日：2023-02-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang-An Huang ,  Ming-Hua Tsai ,  Wen-Fang Lee ,  Chin-Chia Kuo ,  Jung Han ,  Chun-Lin Chen ,  Ching-Chung Yang ,  Nien-Chung Li

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7835 ,  H01L29/1033 ,  H01L29/42364 ,  H01L29/7801

Abstract: An extended drain metal oxide semiconductor transistor includes a substrate. A gate is disposed on the substrate. A source doped region is disposed in the substrate at one side of the gate. A drain doped region is disposed in the substrate at another side of the gate. A thin gate dielectric layer is disposed under the gate. A thick gate dielectric layer is disposed under the gate. The thick gate dielectric layer extends from the bottom of the gate to contact the drain doped region. A second conductive type first well is disposed in the substrate and surrounds the source doped region and the drain doped region. A deep well is disposed within the substrate and surrounds the second conductive type first well.

公开(公告)号：US20230261092A1

公开(公告)日：2023-08-17

申请号：US17694694

申请日：2022-03-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsuan Chang ,  Hao-Ping Yan ,  Ming-Hua Tsai ,  Chin-Chia Kuo

IPC: H01L29/66 ,  H01L21/266 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/6659 ,  H01L21/266 ,  H01L29/7833 ,  H01L29/0607

Abstract: A fabricating method of a middle voltage transistor includes providing a substrate. A gate predetermined region is defined on the substrate. Next, a mask layer is formed to cover only part of the gate predetermined region. Then, a first ion implantation process is performed to implant dopants into the substrate at two sides of the mask layer to form two first lightly doping regions. After removing the mask layer, a gate is formed to overlap the entirety gate predetermined region. Subsequently, two second lightly doping regions respectively formed within one of the first lightly doping regions. Next, two source/drain doping regions are respectively formed within one of the second lightly doping regions. Finally, two silicide layers are formed to respectively cover one of the source/drain doping regions.

公开(公告)号：US20210217705A1

公开(公告)日：2021-07-15

申请号：US16737928

申请日：2020-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsuan Chang ,  Ming-Hua Tsai ,  Chin-Chia Kuo

IPC: H01L23/00 ,  H01L49/02 ,  H01L23/522 ,  H01L27/08 ,  H01L21/762 ,  H01L27/06

Abstract: A semiconductor device includes a substrate, a first isolation structure, a second isolation structure and a dummy pattern. The substrate includes a first part surrounding a second part at a top view. The first isolation structure is disposed between the first part and the second part, to isolate the first part from the second part. The second isolation structure is disposed at at least one corner of the first part. The dummy pattern is disposed on the second isolation structure. The present invention also provides a method of forming said semiconductor device.

公开(公告)号：US10068793B1

公开(公告)日：2018-09-04

申请号：US15614075

申请日：2017-06-05

Applicant: United Microelectronics Corp.

Inventor： Chin-Chia Kuo ,  Ming-Hua Tsai

IPC: H01L21/70 ,  H01L21/762 ,  H01L29/06 ,  H01L21/311 ,  H01L21/28 ,  H01L21/768

Abstract: A semiconductor structure including a substrate, an isolation structure, a first gate structure, a second gate structure and a protection layer is provided. The isolation structure is disposed on the substrate. The first gate structure and the second gate structure are adjacent to each other and disposed on the isolation structure. Each of the first gate structure and the second gate structure includes a conductive layer. The protection layer is disposed between the first gate structure and the second gate structure and covers the isolation structure between the first gate structure and the second gate structure.

公开(公告)号：US20240266435A1

公开(公告)日：2024-08-08

申请号：US18120980

申请日：2023-03-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Tsai ,  Chin-Chia Kuo ,  Wei-Hsuan Chang

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7835 ,  H01L29/6659

Abstract: A transistor with an embedded insulating structure set includes a substrate. A gate is disposed on the substrate. A first lightly doped region is disposed at one side of the gate. A second lightly doped region is disposed at another side of the gate. The first lightly doped region and the second lightly doped region have the same conductive type. The first lightly doped region is symmetrical to the second lightly doped region. A first source/drain doped region is disposed within the first lightly doped region. A second source/drain doped region is disposed within the second lightly doped region. A first insulating structure set is disposed within the first lightly doped region and the first source/drain doped region. The first insulating structure set includes an insulating block embedded within the substrate. A sidewall of the insulating block contacts the gate dielectric layer.