公开(公告)号：US11348847B2

公开(公告)日：2022-05-31

申请号：US16249812

申请日：2019-01-16

Applicant: United Microelectronics Corp.

Inventor： Kun-Yuan Wu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Chen-Hsien Hsu ,  Yuan-Hui Chen ,  Ruei-Yau Chen ,  Cheng-Tsung Ku ,  Zhi-Hong Huang ,  Cheng-Yang Tsai ,  Yu-Lin Chen

IPC: H01L21/66 ,  G01R31/28 ,  H03K3/03 ,  H01L23/544

Abstract: The invention provides a testkey detection circuit, including a plurality of oscillators and a driving circuit. Each of the oscillators has an enable terminal, a voltage terminal and an output terminal, wherein the enable terminals are connected to a common enable terminal. The driving circuit receives the output terminals of the oscillators and increases a driving level of a selected one of the output terminals as a frequency output.

公开(公告)号：US11115033B1

公开(公告)日：2021-09-07

申请号：US17065414

申请日：2020-10-07

Applicant: United Microelectronics Corp.

Inventor： Kun-Yuan Wu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Cheng-Yang Tsai ,  Ruei-Yau Chen ,  Yu-Lin Chen

IPC: H03L7/089 ,  H03L7/099

Abstract: A speed-up charge pump includes a first charge pump for receiving an up signal and a down signal in digital form to produce a first voltage control signal at an output node. Further, at least one speed-up phase detector includes a first circuit path to receive the up signal and delay the up signal by a predetermined delay as a delay up signal and operate the up signal and the delay up signal by AND logic into an auxiliary up signal; and a second circuit path to receive the down signal and delay the down signal by the predetermined delay as a delay down signal and operate the down signal and the delay down signal by AND logic into an auxiliary down signal. A second charge pump is respectively receiving the auxiliary up and down signals to produce a second voltage control signal also at the output node.

公开(公告)号：US20210288634A1

公开(公告)日：2021-09-16

申请号：US16847682

申请日：2020-04-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Yuan Wu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Chen-Hsien Hsu ,  Yuan-Hui Chen ,  Cheng-Yang Tsai ,  Ruei-Yau Chen ,  Cheng-Tsung Ku ,  Zhi-Hong Huang ,  Yu-Lin Chen

IPC: H03K5/13

Abstract: A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.

公开(公告)号：US11368146B2

公开(公告)日：2022-06-21

申请号：US16847682

申请日：2020-04-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Yuan Wu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Chen-Hsien Hsu ,  Yuan-Hui Chen ,  Cheng-Yang Tsai ,  Ruei-Yau Chen ,  Cheng-Tsung Ku ,  Zhi-Hong Huang ,  Yu-Lin Chen

IPC: H03K5/13 ,  H03K5/00

Abstract: A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.