公开(公告)号：US20130330919A1

公开(公告)日：2013-12-12

申请号：US13960812

申请日：2013-08-07

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Kun-Hsien LIN ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L21/28 ,  H01L29/40

CPC classification number: H01L21/31144 ,  H01L21/28008 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

Abstract: A manufacturing process of an etch stop layer is provided. The manufacturing process includes steps of providing a substrate; forming a gate stack structure over the substrate, wherein the gate stack structure at least comprises a dummy polysilicon layer and a barrier layer; removing the dummy polysilicon layer to define a trench and expose a surface of the barrier layer; forming a repair layer on the surface of the barrier layer and an inner wall of the trench; and forming an etch stop layer on the repair layer. In addition, a manufacturing process of the gate stack structure with the etch stop layer further includes of forming an N-type work function metal layer on the etch stop layer within the trench, and forming a gate layer on the N-type work function metal layer within the trench.

公开(公告)号：US09190292B2

公开(公告)日：2015-11-17

申请号：US14722174

申请日：2015-05-27

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Kun-Hsien Lin ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L29/78 ,  H01L21/311 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L29/40

CPC classification number: H01L21/31144 ,  H01L21/28008 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

Abstract: A manufacturing process of an etch stop layer is provided. The manufacturing process includes steps of providing a substrate; forming a gate stack structure over the substrate, wherein the gate stack structure at least comprises a dummy polysilicon layer and a barrier layer; removing the dummy polysilicon layer to define a trench and expose a surface of the barrier layer; forming a repair layer on the surface of the barrier layer and an inner wall of the trench; and forming an etch stop layer on the repair layer. In addition, a manufacturing process of the gate stack structure with the etch stop layer further includes of forming an N-type work function metal layer on the etch stop layer within the trench, and forming a gate layer on the N-type work function metal layer within the trench.

公开(公告)号：US20150093893A1

公开(公告)日：2015-04-02

申请号：US14044855

申请日：2013-10-02

Applicant: United Microelectronics Corporation

Inventor： Yi-Fang Tao ,  Ching-Wei Hsu ,  Hsin-Yu Chen ,  Tsun-Min Cheng ,  Yung-Chien Kung ,  Chi-Mao Hsu ,  Guo-Wei Chen ,  Huei-Ru Tsai ,  Jia-Rong Li

IPC: H01L21/768

CPC classification number: H01L21/76864 ,  H01L21/76873 ,  H01L21/76882

Abstract: In a process of forming a seed layer, particularly in a vertical trench or via, a semiconductor substrate having a dielectric structure and a hard mask structure thereon is provided. An opening is formed in the hard mask structure, and a trench or via is formed in the dielectric structure in communication with the opening, wherein an area of the opening is greater than that of an entrance of the trench or via. A seed layer is then deposited in the trench or via through the opening, and then subjected to a reflow process.

Abstract translation: 在形成种子层的过程中，特别是在垂直沟槽或通孔中，提供了具有电介质结构和硬掩模结构的半导体衬底。 在硬掩模结构中形成开口，并且在与开口连通的电介质结构中形成沟槽或通孔，其中开口的面积大于沟槽或通孔的入口面积。 然后将种子层沉积在沟槽或通孔中通过开口，然后进行回流处理。

公开(公告)号：US09087782B2

公开(公告)日：2015-07-21

申请号：US13960812

申请日：2013-08-07

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Kun-Hsien Lin ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L21/31144 ,  H01L21/28008 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

Abstract: A manufacturing process of an etch stop layer is provided. The manufacturing process includes steps of providing a substrate; forming a gate stack structure over the substrate, wherein the gate stack structure at least comprises a dummy polysilicon layer and a barrier layer; removing the dummy polysilicon layer to define a trench and expose a surface of the barrier layer; forming a repair layer on the surface of the barrier layer and an inner wall of the trench; and forming an etch stop layer on the repair layer. In addition, a manufacturing process of the gate stack structure with the etch stop layer further includes of forming an N-type work function metal layer on the etch stop layer within the trench, and forming a gate layer on the N-type work function metal layer within the trench.

Abstract translation: 提供蚀刻停止层的制造工艺。 制造方法包括提供基板的步骤; 在所述衬底上形成栅极叠层结构，其中所述栅极堆叠结构至少包括虚设多晶硅层和阻挡层; 去除所述虚设多晶硅层以限定沟槽并暴露所述阻挡层的表面; 在阻挡层的表面和沟槽的内壁上形成修复层; 以及在修复层上形成蚀刻停止层。 此外，具有蚀刻停止层的栅极堆叠结构的制造工艺还包括在沟槽内的蚀刻停止层上形成N型功函数金属层，并且在N型功函数金属上形成栅极层 沟内的层。