公开(公告)号：US10530258B1

公开(公告)日：2020-01-07

申请号：US16392664

申请日：2019-04-24

Applicant: University of Electronic Science and Technology of China

Inventor： Zekun Zhou ,  Yunkun Wang ,  Yandong Yuan ,  Shilei Li ,  Zhuo Wang ,  Bo Zhang

IPC: H02M1/38 ,  H02M3/158 ,  H02M1/00 ,  H02M3/156

Abstract: A predictive dead time generating circuit includes a dead time detecting module configured to detect a dead time between the switching off of the upper power transistor and the switching on of the lower power transistor, and a dead time between the switching off of the lower power transistor and the switching on of the upper power transistor, and to generate a first detecting signal and a second detecting signal according to the condition of whether the detected dead time reaches an optimal value. The logic control module changes the output of the delay module according to the judgment result of the dead time detecting module, so as to change the dead time between the driving signal of the upper power transistor and the driving signal of the lower power transistor.

公开(公告)号：US10042379B1

公开(公告)日：2018-08-07

申请号：US15867717

申请日：2018-01-11

Applicant: University of Electronic Science and Technology of China

Inventor： Zekun Zhou ,  Xiang Li ,  Yandong Yuan ,  Yue Shi ,  Zhuo Wang ,  Bo Zhang

IPC: H03K3/42 ,  G05F3/26

Abstract: A sub-threshold low-power and resistor-less reference circuit which is related to the field of reference circuit technology of analog circuit includes a negative-temperature-coefficient voltage generating circuit, a positive-temperature-coefficient voltage generating circuit and a current balancing circuit. The negative-temperature-coefficient voltage generating circuit generates a negative-temperature-coefficient voltage VCTAT based on the negative-temperature voltage characteristic of base-emitter PN junction of the bipolar tsansistor. On the other hand, the positive-temperature-coefficient voltage generating circuit generates a positive-temperature-coefficient voltage VPTAT based on the positive-temperature voltage characteristic of the NMOS transistor operating in a sub-threshold region. The current balancing circuit is configured to eliminate the error current caused due to the difference of the current mirror when the two voltages with different temperature characteristics are superposed to output a reference voltage.