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    System for placement optimization of chip design for transient noise control and related methods thereof
    3.
    发明授权
    System for placement optimization of chip design for transient noise control and related methods thereof 有权

    公开(公告)号：US11436401B2

    公开(公告)日：2022-09-06

    申请号：US16571773

    申请日：2019-09-16

    Applicant: UNIVERSITY OF VIRGINIA PATENT FOUNDATION

    Inventor： Ke Wang ,  Kevin Skadron ,  Mircea R. Stan ,  Runjie Zhang

    IPC: G06F30/39 ,  G06F30/367 ,  G06F30/392 ,  G06F119/10

    Abstract: Transient voltage noise, including resistive and reactive noise, causes timing errors at runtime. A heuristic framework, Walking Pads, is introduced to minimize transient voltage violations by optimizing power supply pad placement. It is shown that the steady-state optimal design point differs from the transient optimum, and further noise reduction can be achieved with transient optimization. The methodology significantly reduces voltage violations by balancing the average transient voltage noise of the four branches at each pad site. When pad placement is optimized using a representative stressmark, voltage violations are reduced 46-80% across 11 Parsec benchmarks with respect to the results from IR-drop-optimized pad placement. It is shown that the allocation of on-chip decoupling capacitance significantly influences the optimal locations of pads.

    Disjunctive rule mining with finite automaton hardware
    4.
    发明授权
    Disjunctive rule mining with finite automaton hardware 有权

    公开(公告)号：US10474690B2

    公开(公告)日：2019-11-12

    申请号：US15475819

    申请日：2017-03-31

    Applicant: UNIVERSITY OF VIRGINIA PATENT FOUNDATION

    Inventor： Ke Wang ,  Kevin Skadron ,  Elaheh Sadredini

    IPC: G06F17/30 ,  G06F16/2458

    Abstract: The present invention introduces the development of a flexible CPU-AP (Computer Processing Unit-Automata Processor) computing infrastructure for mining hierarchical patterns based on Apriori algorithm. A novel automaton design strategy, called linear design, is described to generate automata for matching and counting hierarchical patterns and apply it on SPM (Sequential Pattern Mining). In addition, another novel automaton design strategy, called reduction design, is described for the disjunctive rule matching (DRM) and counting. The present invention shows performance improvement of AP SPM and DRM solutions and broader capability over multicore and GPU (Graphics Processing Unit) implementations of GSP SPM, and shows that AP SPM and DRM solutions outperform state-of-the-art SPM algorithms SPADE and PrefixSpan (especially for larger datasets).

    Association rule mining with the micron automata processor
    5.
    发明授权
    Association rule mining with the micron automata processor 有权

    公开(公告)号：US10445323B2

    公开(公告)日：2019-10-15

    申请号：US14871457

    申请日：2015-09-30

    Applicant: UNIVERSITY OF VIRGINIA PATENT FOUNDATION

    Inventor： Ke Wang ,  Kevin Skadron

    IPC: G06F16/245 ,  G06F16/2458

    Abstract: The present invention discloses a heterogeneous computation framework, of Association. Rule Mining (ARM) using Micron's Autotmata Processor (AP). This framework is based on the Apriori algorithm. Two Automaton designs are proposed to match and count the individual itemset. Several performance improvement strategies are proposed including minimizing the number of reporting vectors and reduce reconfiguration delays. The experiment results show up to 94× speed ups of the proposed AP-accelerated Apriori on six synthetic and real-world datasets, when compared with the Apriori single-core CPU implementation. The proposed AP-accelerated Apriori solution also outperforms the state-of-the-art multicore and GPU implementations of Equivalence Class Transformation (Eclat) algorithm on big datasets.

    DISJUNCTIVE RULE MINING WITH FINITE AUTOMATON HARDWARE
    6.
    发明申请
    DISJUNCTIVE RULE MINING WITH FINITE AUTOMATON HARDWARE 审中-公开

    公开(公告)号：US20180285424A1

    公开(公告)日：2018-10-04

    申请号：US15475819

    申请日：2017-03-31

    Applicant: UNIVERSITY OF VIRGINIA PATENT FOUNDATION

    Inventor： Ke Wang ,  Kevin Skadron ,  Elaheh Sadredini

    IPC: G06F17/30

    CPC classification number: G06F16/2465

    Abstract: The present invention introduces the development of a flexible CPU-AP (Computer Processing Unit-Automata Processor) computing infrastructure for mining hierarchical patterns based on Apriori algorithm. A novel automaton design strategy, called linear design, is described to generate automata for matching and counting hierarchical patterns and apply it on SPM (Sequential Pattern Mining). In addition, another novel automaton design strategy, called reduction design, is described for the disjunctive rule matching (DRM) and counting. The present invention shows performance improvement of AP SPM and DRM solutions and broader capability over multicore and GPU (Graphics Processing Unit) implementations of GSP SPM, and shows that AP SPM and DRM solutions outperform state-of-the-art SPM algorithms SPADE and PrefixSpan (especially for larger datasets).

    SEQUENTIAL PATTERN MINING WITH THE MICRON AUTOMATA PROCESSOR
    7.
    发明申请
    SEQUENTIAL PATTERN MINING WITH THE MICRON AUTOMATA PROCESSOR 审中-公开

    公开(公告)号：US20170293670A1

    公开(公告)日：2017-10-12

    申请号：US15198521

    申请日：2016-06-30

    Applicant: University of Virginia Patent Foundation

    Inventor： Ke Wang ,  Elaheh Sadredini ,  Kevin Skadron

    IPC: G06F17/30 ,  G06N5/04

    CPC classification number: G06N5/047 ,  G06K9/00986 ,  G06K9/68 ,  G06N7/005

    Abstract: A hardware accelerated solution of the SPM (Sequential Pattern Mining) is proposed using Micron's Automata Processor (AP), a hardware implementation of non-deterministic finite automata (NFAs) The Generalized Sequential Pattern (GSP) algorithm for SPM searching exposes massive parallelism, and is therefore well-suited for AP acceleration. The multi puss pruning strategy of the GSP is implemented is the APs fast reconfigurability. A generalized automaton structure is proposed by flattening sequential patterns to simple strings to reduce compilation time and to minimize overhead of reconfiguration. Up to 90× and 29× speedups are achieved by the AP-accelerated GSP on six real-world datasets, when compared with the optimized multicore CPU (Central Processing Unit) and GPU (Graphics Processing Unit) GSP implementations, respectively. The proposed CPU-AP solution also outperforms the state-of-the-art PrefixSpan and SPADE (Sequential PAttern Discovery using Equivalence classes algorithms on multicore CPU by up to 452× and 49× speedups.

    SYSTEM FOR PLACEMENT OPTIMIZATION OF CHIP DESIGN FOR TRANSIENT NOISE CONTROL AND RELATED METHODS THEREOF
    8.
    发明申请
    SYSTEM FOR PLACEMENT OPTIMIZATION OF CHIP DESIGN FOR TRANSIENT NOISE CONTROL AND RELATED METHODS THEREOF 审中-公开
    用于过渡噪声控制的芯片设计的放置优化系统及其相关方法

    公开(公告)号：US20150370944A1

    公开(公告)日：2015-12-24

    申请号：US14727277

    申请日：2015-06-01

    Applicant: UNIVERSITY OF VIRGINIA PATENT FOUNDATION

    Inventor： Ke Wang ,  Kevin Skadron ,  Mircea R. Stan ,  Runjie Zhang

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  G06F17/5036 ,  G06F17/5072 ,  G06F2217/82

    Abstract: Transient voltage noise, including resistive and reactive noise, causes timing errors at runtime. A heuristic framework, Walking Pads, is introduced to minimize transient voltage violations by optimizing power supply pad placement. It is shown that the steady-state optimal design point differs from the transient optimum, and further noise reduction can be achieved with transient optimization. The methodology significantly reduces voltage violations by balancing the average transient voltage noise of the four branches at each pad site. When pad placement is optimized using a representative stressmark, voltage violations are reduced 46-80% across 11 Parsec benchmarks with respect to the results from IR-drop-optimized pad placement. It is shown that the allocation of on-chip decoupling capacitance significantly influences the optimal locations of pads.

    Abstract translation: 包括电阻和无功噪声在内的瞬态电压噪声会在运行时产生定时误差。 引入了启发式框架，步进垫，通过优化电源垫放置来最小化瞬态电压违规。 表明稳态最优设计点与瞬态最优值不同，可以通过瞬态优化实现进一步的降噪。 该方法通过平衡每个焊盘位置处四个分支的平均瞬态电压噪声来显着降低电压违规。 当使用代表性的压力标记来优化焊盘放置时，相对于IR降低优化的焊盘放置的结果，11次Parsec基准电压违规将降低46-80％。 显示片上去耦电容的分配显着影响焊盘的最佳位置。

    SYSTEM FOR PLACEMENT OPTIMIZATION OF CHIP DESIGN FOR TRANSIENT NOISE CONTROL AND RELATED METHODS THEREOF
    10.
    发明申请
    SYSTEM FOR PLACEMENT OPTIMIZATION OF CHIP DESIGN FOR TRANSIENT NOISE CONTROL AND RELATED METHODS THEREOF 审中-公开

    公开(公告)号：US20200151380A1

    公开(公告)日：2020-05-14

    申请号：US16571773

    申请日：2019-09-16

    Applicant: UNIVERSITY OF VIRGINIA PATENT FOUNDATION

    Inventor： Ke Wang ,  Kevin Skadron ,  Mircea R. Stan ,  Runjie Zhang

    IPC: G06F30/39 ,  G06F30/392 ,  G06F30/367

    Abstract: Transient voltage noise, including resistive and reactive noise, causes timing errors at runtime. A heuristic framework, Walking Pads, is introduced to minimize transient voltage violations by optimizing power supply pad placement. It is shown that the steady-state optimal design point differs from the transient optimum, and further noise reduction can be achieved with transient optimization. The methodology significantly reduces voltage violations by balancing the average transient voltage noise of the four branches at each pad site. When pad placement is optimized using a representative stressmark, voltage violations are reduced 46-80% across 11 Parsec benchmarks with respect to the results from IR-drop-optimized pad placement. It is shown that the allocation of on-chip decoupling capacitance significantly influences the optimal locations of pads.

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