公开(公告)号：US20210028818A1

公开(公告)日：2021-01-28

申请号：US16947249

申请日：2020-07-24

Applicant: University of Virginia Patent Foundation

Inventor： Mircea R. Stan ,  Luisa P. Gonzalez Guerrero

IPC: H04B1/7163 ,  H04B14/06 ,  H03M3/00

Abstract: Asynchronous stream generation and processing techniques are described that support implementation of an asynchronous stream mote in which one or more analog sensor signals are used to generate one or more asynchronous streams. On-device operations processing of the one or more asynchronous streams may be performed before transmission of the result(s) to other system components (e.g., peer motes or higher-level system components).

公开(公告)号：US11451261B2

公开(公告)日：2022-09-20

申请号：US16947249

申请日：2020-07-24

Applicant: University of Virginia Patent Foundation

Inventor： Mircea R. Stan ,  Luisa P. Gonzalez Guerrero

IPC: H04B1/7163 ,  H03M3/00 ,  H04B14/06 ,  H04W84/18

Abstract: Asynchronous stream generation and processing techniques are described that support implementation of an asynchronous stream mote in which one or more analog sensor signals are used to generate one or more asynchronous streams. On-device operations processing of the one or more asynchronous streams may be performed before transmission of the result(s) to other system components (e.g., peer motes or higher-level system components).

公开(公告)号：US20150370944A1

公开(公告)日：2015-12-24

申请号：US14727277

申请日：2015-06-01

Applicant: UNIVERSITY OF VIRGINIA PATENT FOUNDATION

Inventor： Ke Wang ,  Kevin Skadron ,  Mircea R. Stan ,  Runjie Zhang

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5036 ,  G06F17/5072 ,  G06F2217/82

Abstract: Transient voltage noise, including resistive and reactive noise, causes timing errors at runtime. A heuristic framework, Walking Pads, is introduced to minimize transient voltage violations by optimizing power supply pad placement. It is shown that the steady-state optimal design point differs from the transient optimum, and further noise reduction can be achieved with transient optimization. The methodology significantly reduces voltage violations by balancing the average transient voltage noise of the four branches at each pad site. When pad placement is optimized using a representative stressmark, voltage violations are reduced 46-80% across 11 Parsec benchmarks with respect to the results from IR-drop-optimized pad placement. It is shown that the allocation of on-chip decoupling capacitance significantly influences the optimal locations of pads.

Abstract translation: 包括电阻和无功噪声在内的瞬态电压噪声会在运行时产生定时误差。 引入了启发式框架，步进垫，通过优化电源垫放置来最小化瞬态电压违规。 表明稳态最优设计点与瞬态最优值不同，可以通过瞬态优化实现进一步的降噪。 该方法通过平衡每个焊盘位置处四个分支的平均瞬态电压噪声来显着降低电压违规。 当使用代表性的压力标记来优化焊盘放置时，相对于IR降低优化的焊盘放置的结果，11次Parsec基准电压违规将降低46-80％。 显示片上去耦电容的分配显着影响焊盘的最佳位置。

公开(公告)号：US11049551B2

公开(公告)日：2021-06-29

申请号：US16682151

申请日：2019-11-13

Applicant: University of Virginia Patent Foundation

Inventor： Marzieh Lenjani ,  Patricia Gonzalez ,  Mircea R. Stan ,  Kevin Skadron

IPC: G06F7/57 ,  G11C11/4093 ,  G11C11/408 ,  G06F13/16 ,  G11C11/4096

Abstract: A method of processing data in a memory can include accessing an array of memory cells located on a semiconductor memory die to provide a row of data including n bits, latching the n bits in one or more row buffer circuits adjacent to the array of memory cells on the semiconductor memory die to provide latched n bits operatively coupled to a column address selection circuit on the semiconductor memory die to provide a portion of the n latched bits as data output from the semiconductor memory die responsive to a memory read operation, and serially transferring the latched n bits in the row buffer circuit to an arithmetic logic unit (ALU) circuit located adjacent to the row buffer circuit on the semiconductor memory die.

公开(公告)号：US20200151380A1

公开(公告)日：2020-05-14

申请号：US16571773

申请日：2019-09-16

Applicant: UNIVERSITY OF VIRGINIA PATENT FOUNDATION

Inventor： Ke Wang ,  Kevin Skadron ,  Mircea R. Stan ,  Runjie Zhang

IPC: G06F30/39 ,  G06F30/392 ,  G06F30/367

Abstract: Transient voltage noise, including resistive and reactive noise, causes timing errors at runtime. A heuristic framework, Walking Pads, is introduced to minimize transient voltage violations by optimizing power supply pad placement. It is shown that the steady-state optimal design point differs from the transient optimum, and further noise reduction can be achieved with transient optimization. The methodology significantly reduces voltage violations by balancing the average transient voltage noise of the four branches at each pad site. When pad placement is optimized using a representative stressmark, voltage violations are reduced 46-80% across 11 Parsec benchmarks with respect to the results from IR-drop-optimized pad placement. It is shown that the allocation of on-chip decoupling capacitance significantly influences the optimal locations of pads.

公开(公告)号：US10417367B2

公开(公告)日：2019-09-17

申请号：US14727277

申请日：2015-06-01

Applicant: UNIVERSITY OF VIRGINIA PATENT FOUNDATION

Inventor： Ke Wang ,  Kevin Skadron ,  Mircea R. Stan ,  Runjie Zhang

IPC: G06F17/50

Abstract: Transient voltage noise, including resistive and reactive noise, causes timing errors at runtime. A heuristic framework, Walking Pads, is introduced to minimize transient voltage violations by optimizing power supply pad placement. It is shown that the steady-state optimal design point differs from the transient optimum, and further noise reduction can be achieved with transient optimization. The methodology significantly reduces voltage violations by balancing the average transient voltage noise of the four branches at each pad site. When pad placement is optimized using a representative stressmark, voltage violations are reduced 46-80% across 11 Parsec benchmarks with respect to the results from IR-drop-optimized pad placement. It is shown that the allocation of on-chip decoupling capacitance significantly influences the optimal locations of pads.

公开(公告)号：US11436401B2

公开(公告)日：2022-09-06

申请号：US16571773

申请日：2019-09-16

Applicant: UNIVERSITY OF VIRGINIA PATENT FOUNDATION

Inventor： Ke Wang ,  Kevin Skadron ,  Mircea R. Stan ,  Runjie Zhang

IPC: G06F30/39 ,  G06F30/367 ,  G06F30/392 ,  G06F119/10

Abstract: Transient voltage noise, including resistive and reactive noise, causes timing errors at runtime. A heuristic framework, Walking Pads, is introduced to minimize transient voltage violations by optimizing power supply pad placement. It is shown that the steady-state optimal design point differs from the transient optimum, and further noise reduction can be achieved with transient optimization. The methodology significantly reduces voltage violations by balancing the average transient voltage noise of the four branches at each pad site. When pad placement is optimized using a representative stressmark, voltage violations are reduced 46-80% across 11 Parsec benchmarks with respect to the results from IR-drop-optimized pad placement. It is shown that the allocation of on-chip decoupling capacitance significantly influences the optimal locations of pads.

公开(公告)号：US20210142846A1

公开(公告)日：2021-05-13

申请号：US16682151

申请日：2019-11-13

Applicant: University of Virginia Patent Foundation

Inventor： Marzieh Lenjani ,  Patricia Gonzalez ,  Mircea R. Stan ,  Kevin Skadron

IPC: G11C11/4093 ,  G06F7/57 ,  G11C11/4096 ,  G11C11/408 ,  G06F13/16

Abstract: A method of processing data in a memory can include accessing an array of memory cells located on a semiconductor memory die to provide a row of data including n bits, latching the n bits in one or more row buffer circuits adjacent to the array of memory cells on the semiconductor memory die to provide latched n bits operatively coupled to a column address selection circuit on the semiconductor memory die to provide a portion of the n latched bits as data output from the semiconductor memory die responsive to a memory read operation, and serially transferring the latched n bits in the row buffer circuit to an arithmetic logic unit (ALU) circuit located adjacent to the row buffer circuit on the semiconductor memory die.