公开(公告)号：US20140208149A1

公开(公告)日：2014-07-24

申请号：US13757575

申请日：2013-02-01

Applicant: VIA Technologies, Inc.

Inventor： Vanessa S. Canac ,  James R. Lundberg

IPC: G06F1/12

CPC classification number: G11C7/1072 ,  G06F1/12 ,  G06F13/3625 ,  G06F13/4068 ,  G06F13/4217 ,  G06F13/4243 ,  G11C8/18

Abstract: An apparatus including a synchronous lag receiver that receives one of a plurality of radially distributed strobes and a data bit, and that delays registering of the data bit by a propagation time. The synchronous lag receiver has a first plurality of matched inverters, a first mux, and a bit receiver. The first plurality of matched inverters generates successively delayed versions of the data bit. The first mux receives a value on a lag bus that indicates the propagation time, and selects one of the successively delayed versions of the data bit that corresponds to the value. The bit receiver receives the one of the successively delayed versions of the data bit and one of a plurality of radially distributed strobe signals, and registers the state of the one of the successively delayed versions of the data bit upon assertion of the one of a plurality of distributed strobe signals.

Abstract translation: 一种装置，包括接收多个径向分布的选通中的一个和数据位的同步延迟接收器，并且延迟数据位的登记传播时间。 同步延迟接收器具有第一多个匹配的反相器，第一复用器和位接收器。 第一多个匹配的逆变器产生数据位的连续延迟版本。 第一复用器在延迟总线上接收指示传播时间的值，并且选择与该值对应的数据位的连续延迟版本中的一个。 位接收器接收数据位的连续延迟版本中的一个和多个径向分布的选通信号中的一个，并且在断言多个数据位之后登记数据位的连续延迟版本中的一个的状态 的分布式选通信号。

公开(公告)号：US20140208147A1

公开(公告)日：2014-07-24

申请号：US13747038

申请日：2013-01-22

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Vanessa S. Canac ,  James R. Lundberg

IPC: G06F1/12

CPC classification number: G06F13/4243 ,  G06F1/12 ,  G06F13/4217 ,  G11C7/1072 ,  G11C8/18

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a bit lag control element and a synchronous lag receiver. The bit lag control element is configured to measure a propagation time beginning with assertion of a strobe and ending with assertion of a first one of a plurality of radially distributed strobes corresponding to the strobe, and is configured to generate a value on a lag bus that indicates the propagation time. The synchronous lag receiver is coupled to the bit lag control element, and is configured to receive the first one of the plurality of radially distributed strobes and a data bit, and is configured to delay registering of the data bit by the propagation time.

Abstract translation: 提供了一种补偿同步数据总线上的未对准的装置。 该装置包括位延迟控制元件和同步滞后接收器。 比特滞后控制元件被配置为测量从选通脉冲的断言开始并以对应于选通脉冲的多个径向分布的选通中的第一个的断言结束的传播时间，并且被配置为在滞后总线上产生一个值， 表示传播时间。 同步延迟接收器耦合到位延迟控制元件，并被配置为接收多个径向分布的选通中的第一个选通和数据位，并且被配置为延迟数据位的登记传播时间。

公开(公告)号：US20140207735A1

公开(公告)日：2014-07-24

申请号：US13747140

申请日：2013-01-22

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Vanessa S. Canac ,  James R. Lundberg

IPC: G06F17/30

CPC classification number: G06F17/30581 ,  G06F13/4217

Abstract: An apparatus that compensates for misalignment on a synchronous data bus. The apparatus includes a replica distribution network, a bit lag control element, and a synchronous lag receiver. The replica distribution network receives a first signal, and generates a second signal, where the replica distribution network comprises replicated propagation characteristics of a radial distribution network for a strobe. The bit lag control element is configured to measure a propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a value on a lag bus that indicates the propagation time. The synchronous lag receiver is coupled to the bit lag control element, and is configured to receive a first one of a plurality of radially distributed strobes and a data bit, and is configured to delay registering of the data bit by the propagation time.

Abstract translation: 补偿同步数据总线上的未对准的装置。 该装置包括复制分发网络，位延迟控制元件和同步延迟接收器。 复制分发网络接收第一信号，并且生成第二信号，其中复制分发网络包括用于选通的径向分布网络的复制传播特性。 比特滞后控制元件被配置为测量从第一信号的断言开始并以第二信号的断言结束的传播时间，并且被配置为在指示传播时间的滞后总线上生成值。 同步延迟接收器耦合到位延迟控制元件，并且被配置为接收多个径向分布的选通信号和数据位中的第一个，并被配置为延迟数据位的登记传播时间。

公开(公告)号：US09319035B2

公开(公告)日：2016-04-19

申请号：US13747187

申请日：2013-01-22

Applicant: VIA Technologies, Inc.

Inventor： Vanessa S. Canac ,  James R. Lundberg

IPC: G06F3/00 ,  G06F5/00 ,  G06F13/42 ,  H03K5/06

CPC classification number: H03K5/06

Abstract: An apparatus having a bit lag control element that measures a propagation time beginning with assertion of a first signal and ending with assertion of a second signal, and that generates a first value indicating an adjusted propagation time. The control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control selects one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and generates a second value on a lag select bus that indicates the propagation time. The adjust logic is coupled to a circuit and to the lag select bus, and adjusts the second value by an amount prescribed by the circuit to yield a third value that is output to an adjusted lag bus. The gray encoder gray encodes the third value to generate the first value on the lag bus.

Abstract translation: 一种具有位延迟控制元件的装置，其测量从第一信号的断言开始并以第二信号的断言结束的传播时间，并且生成指示经调整的传播时间的第一值。 控制元件包括延迟锁定控制，调整逻辑和灰度编码器。 延迟锁定控制选择与断言第二信号一致的第一信号的多个连续延迟版本中的一个，并在指示传播时间的延迟选择总线上产生第二值。 调整逻辑耦合到电路和滞后选择总线，并且通过电路规定的量来调整第二值，以产生输出到经调整的滞后总线的第三值。 灰色编码器灰度编码第三个值，以产生滞后总线上的第一个值。

公开(公告)号：US20140208148A1

公开(公告)日：2014-07-24

申请号：US13757480

申请日：2013-02-01

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Vanessa S. Canac ,  James R. Lundberg

IPC: G06F1/12

CPC classification number: G06F13/4243 ,  G06F1/12 ,  G06F13/4217 ,  G11C7/1072 ,  G11C8/18

Abstract: An apparatus including a Joint Test Action Group (JTAG) interface and a bit lag control element. The JTAG interface receives information that indicates an amount to adjust a propagation time. The bit lag control element measures the propagation time beginning with assertion of a first signal and ending with assertion of a second signal, and generates a value indicating an adjusted propagation time. The bit lag control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control selects one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and generates a second value indicating the propagation time. The adjust logic adjusts the second value by the amount prescribed by the JTAG interface to yield a third value. The gray encoder gray encodes the third value to generate the value on the lag bus.

Abstract translation: 一种包括联合测试动作组（JTAG）接口和位滞后控制元件的装置。 JTAG接口接收指示调整传播时间的量的信息。 位延迟控制元件测量从第一信号的断言开始并以第二信号的断言结束的传播时间，并产生指示经调整的传播时间的值。 位延迟控制元件包括延迟锁定控制，调整逻辑和灰度编码器。 延迟锁定控制选择与断言第二信号一致的第一信号的多个连续延迟版本中的一个，并且生成指示传播时间的第二值。 调整逻辑将第二个值调整为由JTAG接口规定的量以产生第三个值。 灰色编码器灰度编码第三个值，以产生滞后总线上的值。

公开(公告)号：US20140204691A1

公开(公告)日：2014-07-24

申请号：US13747187

申请日：2013-01-22

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Vanessa S. Canac ,  James R. Lundberg

IPC: H03K5/159

CPC classification number: H03K5/06

Abstract: An apparatus having a bit lag control element that measures a propagation time beginning with assertion of a first signal and ending with assertion of a second signal, and that generates a first value indicating an adjusted propagation time. The control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control selects one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and generates a second value on a lag select bus that indicates the propagation time. The adjust logic is coupled to a circuit and to the lag select bus, and adjusts the second value by an amount prescribed by the circuit to yield a third value that is output to an adjusted lag bus. The gray encoder gray encodes the third value to generate the first value on the lag bus.

Abstract translation: 一种具有位延迟控制元件的装置，其测量从第一信号的断言开始并以第二信号的断言结束的传播时间，并且生成指示经调整的传播时间的第一值。 控制元件包括延迟锁定控制，调整逻辑和灰度编码器。 延迟锁定控制选择与断言第二信号一致的第一信号的多个连续延迟版本中的一个，并在指示传播时间的延迟选择总线上产生第二值。 调整逻辑耦合到电路和滞后选择总线，并且通过电路规定的量来调整第二值，以产生输出到经调整的滞后总线的第三值。 灰色编码器灰度编码第三个值，以产生滞后总线上的第一个值。

公开(公告)号：US09557765B2

公开(公告)日：2017-01-31

申请号：US13757575

申请日：2013-02-01

Applicant: VIA Technologies, Inc.

Inventor： Vanessa S. Canac ,  James R. Lundberg

IPC: G06F13/42 ,  G06F1/12

CPC classification number: G11C7/1072 ,  G06F1/12 ,  G06F13/3625 ,  G06F13/4068 ,  G06F13/4217 ,  G06F13/4243 ,  G11C8/18

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver that is configured to receive one of a plurality of radially distributed strobes and a data bit, and that is configured to delay registering of the data bit by a propagation time. The replica radial distribution element is configured to receive a first signal, and is configured to generate a second signal, where the replica radial distribution element comprises replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The bit lag control element is configured to measure a propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a value on a lag bus that indicates the propagation time. The synchronous lag receiver has a first plurality of matched inverters, a first mux, and a bit receiver. The first plurality of matched inverters is configured to generate successively delayed versions of the data bit. The first mux is coupled to the first plurality of matched inverters, and is configured to receive a value on a lag bus that indicates the propagation time, and is configured to select one of the successively delayed versions of the data bit that corresponds to the value. The bit receiver is configured to receive the one of the successively delayed versions of the data bit and one of a plurality of radially distributed strobe signals, and is configured to register the state of the one of the successively delayed versions of the data bit upon assertion of the one of a plurality of radially distributed strobe signals.

Abstract translation: 提供了一种补偿同步数据总线上的未对准的装置。 该装置包括复制径向分布元件，位延迟控制元件和同步延迟接收器，其被配置为接收多个径向分布的选通中的一个和数据位，并且被配置为延迟数据位的寄存 传播时间。 复制径向分布元件被配置为接收第一信号，并且被配置为生成第二信号，其中副本径向分布元件包括用于选通脉冲的径向分布网络的复制传播路径长度，负载和缓冲。 比特滞后控制元件被配置为测量从第一信号的断言开始并以第二信号的断言结束的传播时间，并且被配置为在指示传播时间的滞后总线上生成值。 同步延迟接收器具有第一多个匹配的反相器，第一复用器和位接收器。 第一多个匹配的反相器被配置为产生数据位的连续延迟版本。 第一复用器耦合到第一多个匹配的反相器，并且被配置为在延迟总线上接收指示传播时间的值，并且被配置为选择对应于该值的数据位的连续延迟版本中的一个 。 位接收器被配置为接收数据位的连续延迟版本中的一个和多个径向分布的选通信号中的一个，并且被配置为在断言时注册数据位的连续延迟版本中的一个的状态 的多个径向分布的选通信号中的一个。

公开(公告)号：US09552321B2

公开(公告)日：2017-01-24

申请号：US13757480

申请日：2013-02-01

Applicant: VIA Technologies, Inc.

Inventor： Vanessa S. Canac ,  James R. Lundberg

IPC: G06F13/42

CPC classification number: G06F13/4243 ,  G06F1/12 ,  G06F13/4217 ,  G11C7/1072 ,  G11C8/18

Abstract: A method for aligning signals on a bus, including: replicating propagation path lengths, loads, and buffering of a radial distribution network for a strobe; receiving a first signal, and generating a second signal by employing the replicated propagation path lengths, loads, and buffering; receiving control information over a standard JTAG bus, wherein the control information indicates an amount to adjust a propagation time; and measuring the propagation time beginning with assertion of the first signal and ending with assertion of the second signal, said measuring comprising: selecting one of a plurality of successively delayed versions of the first signal that coincides with assertion of the second signal; adjusting the propagation time by the amount prescribed by the control information to yield an adjusted propagation time; and gray encoding the adjusted propagation time to generate a value on a lag bus.

Abstract translation: 一种用于在总线上对准信号的方法，包括：复制用于选通的径向分布网络的传播路径长度，负载和缓冲; 接收第一信号，并通过采用复制的传播路径长度，加载和缓冲来产生第二信号; 通过标准JTAG总线接收控制信息，其中所述控制信息指示调整传播时间的量; 并且测量从所述第一信号的断言开始并以所述第二信号的断言结束的所述传播时间，所述测量包括：选择与所述第二信号的断言一致的所述第一信号的多个连续延迟版本中的一个; 将传播时间调整为由控制信息规定的量，以产生经调整的传播时间; 并且对经调整的传播时间灰度编码以在滞后总线上产生一个值。

公开(公告)号：US08886855B2

公开(公告)日：2014-11-11

申请号：US13747140

申请日：2013-01-22

Applicant: VIA Technologies, Inc.

Inventor： Vanessa S. Canac ,  James R. Lundberg

IPC: G06F13/00 ,  G06F17/30 ,  G06F13/42

CPC classification number: G06F17/30581 ,  G06F13/4217

Abstract: An apparatus that compensates for misalignment on a synchronous data bus. The apparatus includes a replica distribution network, a bit lag control element, and a synchronous lag receiver. The replica distribution network receives a first signal, and generates a second signal, where the replica distribution network comprises replicated propagation characteristics of a radial distribution network for a strobe. The bit lag control element is configured to measure a propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a value on a lag bus that indicates the propagation time. The synchronous lag receiver is coupled to the bit lag control element, and is configured to receive a first one of a plurality of radially distributed strobes and a data bit, and is configured to delay registering of the data bit by the propagation time.

Abstract translation: 补偿同步数据总线上的未对准的装置。 该装置包括复制分发网络，位延迟控制元件和同步延迟接收器。 复制分发网络接收第一信号，并且生成第二信号，其中复制分发网络包括用于选通的径向分布网络的复制传播特性。 比特滞后控制元件被配置为测量从第一信号的断言开始并以第二信号的断言结束的传播时间，并且被配置为在指示传播时间的滞后总线上生成值。 同步延迟接收器耦合到位延迟控制元件，并且被配置为接收多个径向分布的选通信号和数据位中的第一个，并被配置为延迟数据位的登记传播时间。

公开(公告)号：US09552320B2

公开(公告)日：2017-01-24

申请号：US13747038

申请日：2013-01-22

Applicant: VIA Technologies, Inc.

Inventor： Vanessa S. Canac ,  James R. Lundberg

IPC: G06F13/42

CPC classification number: G06F13/4243 ,  G06F1/12 ,  G06F13/4217 ,  G11C7/1072 ,  G11C8/18

Abstract: A method that compensates for misalignment on a synchronous data bus. The method includes: replicating propagation path lengths, loads, and buffering of a radial distribution network for a strobe, receiving a lag pulse signal, and generating a replicated strobe signal by employing the replicated propagation path loads lengths, and buffering; measuring the time between assertion of the lag pulse signal and assertion of the replicated strobe signal; on a lag bus, generating a value that indicates the time; within a synchronous lag receiver, receiving a first one of a plurality of radially distributed strobes and a data bit, and delaying registering of the data bit by the time.

Abstract translation: 补偿同步数据总线上的未对准的方法。 该方法包括：复制用于选通的径向分布网络的传播路径长度，负载和缓冲，接收延迟脉冲信号，以及通过采用复制的传播路径负载长度和缓冲来产生复制的选通信号; 测量滞后脉冲信号的断言与复制的选通信号的断言之间的时间; 在滞后总线上产生一个表示时间的值; 在同步延迟接收器内，接收多个径向分布的选通信号中的第一个选通信号和数据位，并延迟数据位的记录。