公开(公告)号：US20140361819A1

公开(公告)日：2014-12-11

申请号：US14202275

申请日：2014-03-10

Applicant: VIA TECHNOLOGIES, INC.

Inventor： James R. Lundberg

IPC: H03K17/22 ,  H03K17/16

CPC classification number: H03K17/22 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F1/3296 ,  H03K17/16 ,  H03K19/0008 ,  H03K19/0016 ,  H03K2217/0036 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D50/20

Abstract: A digital power gating system for performing power gating to reduce a voltage of a gated supply bus to a state retention voltage level that reduces leakage current while retaining a digital state of a functional circuit. The power gating system includes gating devices and a power gating control system. Each gating device has current terminals coupled between a global supply bus and the gated supply bus, and a control terminal controlled by a bit of a digital control value. The power gating control system successively adjusts the digital control value to reduce a voltage of the gated supply bus to the state retention voltage level. Adjustment gain and/or adjustment periods may be changed, such as when the digital control value reaches certain values or when the gated supply reaches certain voltage levels. Various parameters are programmable to adjust for particular configurations or to achieve desired operation.

Abstract translation: 一种用于执行电力门控以将门控电源总线的电压降低到保持功能电路的数字状态的同时降低漏电流的状态保持电压电平的数字电源门控系统。 电源门控系统包括门控设备和电源门控控制系统。 每个选通装置具有耦合在全局电源总线和门控电源总线之间的电流端子，以及由位数位控制值控制的控制端子。 电源门控控制系统连续调整数字控制值，将门控电源总线的电压降至状态保持电压电平。 可以改变调节增益和/或调整周期，例如当数字控制值达到某些值时或当门控电源达到一定的电压电平时。 可以对各种参数进行编程以针对特定配置进行调整或实现​​期望的操作。

公开(公告)号：US09898036B2

公开(公告)日：2018-02-20

申请号：US15389538

申请日：2016-12-23

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Vanessa Canac ,  James R. Lundberg

IPC: G06F1/12 ,  G06F13/42

CPC classification number: G06F13/4243 ,  G06F1/12 ,  G06F13/4217 ,  G11C7/1072 ,  G11C8/18

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a Joint Test Action Group (JTAG) interface, and a bit lag control element. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network includes replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to adjust a propagation time. The bit lag control element is configured to measure the propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a first value on a lag bus that indicates an adjusted propagation time. The bit lag control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control is configured to select one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and is configured to generate a second value on a lag select bus that indicates the propagation time, where the delay lock control selects the one of a plurality of successively delayed versions of the first signal by incrementing and decrementing bus states of select inputs on a mux, and where the plurality of successively delayed versions includes inputs to the mux, and where the plurality of successively delayed versions includes outputs a first plurality of series-coupled matched inverter pairs. The adjust logic is coupled to the JTAG interface and to the lag select bus, and is configured adjust the second value by the amount prescribed by the JTAG interface to yield a third value that is output to an adjusted lag bus. The gray encoder is configured to gray encode the third value to generate the first value on the lag bus.

公开(公告)号：US20140208149A1

公开(公告)日：2014-07-24

申请号：US13757575

申请日：2013-02-01

Applicant: VIA Technologies, Inc.

Inventor： Vanessa S. Canac ,  James R. Lundberg

IPC: G06F1/12

CPC classification number: G11C7/1072 ,  G06F1/12 ,  G06F13/3625 ,  G06F13/4068 ,  G06F13/4217 ,  G06F13/4243 ,  G11C8/18

Abstract: An apparatus including a synchronous lag receiver that receives one of a plurality of radially distributed strobes and a data bit, and that delays registering of the data bit by a propagation time. The synchronous lag receiver has a first plurality of matched inverters, a first mux, and a bit receiver. The first plurality of matched inverters generates successively delayed versions of the data bit. The first mux receives a value on a lag bus that indicates the propagation time, and selects one of the successively delayed versions of the data bit that corresponds to the value. The bit receiver receives the one of the successively delayed versions of the data bit and one of a plurality of radially distributed strobe signals, and registers the state of the one of the successively delayed versions of the data bit upon assertion of the one of a plurality of distributed strobe signals.

Abstract translation: 一种装置，包括接收多个径向分布的选通中的一个和数据位的同步延迟接收器，并且延迟数据位的登记传播时间。 同步延迟接收器具有第一多个匹配的反相器，第一复用器和位接收器。 第一多个匹配的逆变器产生数据位的连续延迟版本。 第一复用器在延迟总线上接收指示传播时间的值，并且选择与该值对应的数据位的连续延迟版本中的一个。 位接收器接收数据位的连续延迟版本中的一个和多个径向分布的选通信号中的一个，并且在断言多个数据位之后登记数据位的连续延迟版本中的一个的状态 的分布式选通信号。

公开(公告)号：US20140208147A1

公开(公告)日：2014-07-24

申请号：US13747038

申请日：2013-01-22

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Vanessa S. Canac ,  James R. Lundberg

IPC: G06F1/12

CPC classification number: G06F13/4243 ,  G06F1/12 ,  G06F13/4217 ,  G11C7/1072 ,  G11C8/18

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a bit lag control element and a synchronous lag receiver. The bit lag control element is configured to measure a propagation time beginning with assertion of a strobe and ending with assertion of a first one of a plurality of radially distributed strobes corresponding to the strobe, and is configured to generate a value on a lag bus that indicates the propagation time. The synchronous lag receiver is coupled to the bit lag control element, and is configured to receive the first one of the plurality of radially distributed strobes and a data bit, and is configured to delay registering of the data bit by the propagation time.

Abstract translation: 提供了一种补偿同步数据总线上的未对准的装置。 该装置包括位延迟控制元件和同步滞后接收器。 比特滞后控制元件被配置为测量从选通脉冲的断言开始并以对应于选通脉冲的多个径向分布的选通中的第一个的断言结束的传播时间，并且被配置为在滞后总线上产生一个值， 表示传播时间。 同步延迟接收器耦合到位延迟控制元件，并被配置为接收多个径向分布的选通中的第一个选通和数据位，并且被配置为延迟数据位的登记传播时间。

公开(公告)号：US20140207735A1

公开(公告)日：2014-07-24

申请号：US13747140

申请日：2013-01-22

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Vanessa S. Canac ,  James R. Lundberg

IPC: G06F17/30

CPC classification number: G06F17/30581 ,  G06F13/4217

Abstract: An apparatus that compensates for misalignment on a synchronous data bus. The apparatus includes a replica distribution network, a bit lag control element, and a synchronous lag receiver. The replica distribution network receives a first signal, and generates a second signal, where the replica distribution network comprises replicated propagation characteristics of a radial distribution network for a strobe. The bit lag control element is configured to measure a propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a value on a lag bus that indicates the propagation time. The synchronous lag receiver is coupled to the bit lag control element, and is configured to receive a first one of a plurality of radially distributed strobes and a data bit, and is configured to delay registering of the data bit by the propagation time.

Abstract translation: 补偿同步数据总线上的未对准的装置。 该装置包括复制分发网络，位延迟控制元件和同步延迟接收器。 复制分发网络接收第一信号，并且生成第二信号，其中复制分发网络包括用于选通的径向分布网络的复制传播特性。 比特滞后控制元件被配置为测量从第一信号的断言开始并以第二信号的断言结束的传播时间，并且被配置为在指示传播时间的滞后总线上生成值。 同步延迟接收器耦合到位延迟控制元件，并且被配置为接收多个径向分布的选通信号和数据位中的第一个，并被配置为延迟数据位的登记传播时间。

公开(公告)号：US10133701B2

公开(公告)日：2018-11-20

申请号：US15389544

申请日：2016-12-23

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Vanessa Canac ,  James R. Lundberg

IPC: G06F13/42 ,  G06F1/12 ,  G11C8/18 ,  G11C7/10

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a Joint Test Action Group (JTAG) interface, and a bit lag control element. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network includes replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to adjust a propagation time. The bit lag control element is configured to measure, when an update signal is asserted, the propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a first value on a lag bus that indicates an adjusted propagation time. The bit lag control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control is configured to select one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and is configured to generate a second value on a lag select bus that indicates the propagation time, where the delay lock control selects the one of a plurality of successively delayed versions of the first signal by incrementing and decrementing bus states of select inputs on a mux, and where the plurality of successively delayed versions includes inputs to the mux, and where the plurality of successively delayed versions includes outputs a first plurality of series-coupled matched inverter pairs. The adjust logic is coupled to the JTAG interface and to the lag select bus, and is configured adjust the second value by the amount prescribed by the JTAG interface to yield a third value that is output to an adjusted lag bus. The gray encoder is configured to gray encode the third value to generate the first value on the lag bus.

公开(公告)号：US10079047B2

公开(公告)日：2018-09-18

申请号：US15389795

申请日：2016-12-23

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Vanessa Canac ,  James R. Lundberg

IPC: G06F1/12 ,  G11C7/10 ,  G06F13/42 ,  G11C8/18 ,  G06F13/362 ,  G06F13/40

CPC classification number: G11C7/1072 ,  G06F1/12 ,  G06F13/3625 ,  G06F13/4068 ,  G06F13/4217 ,  G06F13/4243 ,  G11C8/18

Abstract: A method is provided that compensates for misalignment on a synchronous data bus. The method includes: replicating propagation path lengths, loads, and buffering of a radial distribution network for a strobe; receiving a first signal, and generating a second signal by employing the replicated propagation path lengths, loads, and buffering; when an update signal is asserted, when an update signal is asserted, measuring a propagation time beginning with assertion of the first signal and ending with assertion of the second signal by selecting one of a plurality of successively delayed versions of the first signal that coincides with the assertion of the second signal, wherein said selecting comprises incrementing and decrementing bus states of select inputs on a mux, wherein the plurality of successively delayed versions of the first signal comprises inputs to the mux; gray encoding a value on a lag bus that indicates the propagation time; and receiving one of a plurality of radially distributed strobes and a data bit, and delaying registering of the data bit by the propagation time. The receiving includes generating successively delayed versions of the data bit; receiving the value on the lag bus, and selecting one of the successively delayed versions of the data bit that corresponds to the value; and registering the state of the one of the successively delayed versions of the data bit upon assertion of one of a plurality of radially distributed strobe signals.

公开(公告)号：US09557765B2

公开(公告)日：2017-01-31

申请号：US13757575

申请日：2013-02-01

Applicant: VIA Technologies, Inc.

Inventor： Vanessa S. Canac ,  James R. Lundberg

IPC: G06F13/42 ,  G06F1/12

CPC classification number: G11C7/1072 ,  G06F1/12 ,  G06F13/3625 ,  G06F13/4068 ,  G06F13/4217 ,  G06F13/4243 ,  G11C8/18

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver that is configured to receive one of a plurality of radially distributed strobes and a data bit, and that is configured to delay registering of the data bit by a propagation time. The replica radial distribution element is configured to receive a first signal, and is configured to generate a second signal, where the replica radial distribution element comprises replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The bit lag control element is configured to measure a propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a value on a lag bus that indicates the propagation time. The synchronous lag receiver has a first plurality of matched inverters, a first mux, and a bit receiver. The first plurality of matched inverters is configured to generate successively delayed versions of the data bit. The first mux is coupled to the first plurality of matched inverters, and is configured to receive a value on a lag bus that indicates the propagation time, and is configured to select one of the successively delayed versions of the data bit that corresponds to the value. The bit receiver is configured to receive the one of the successively delayed versions of the data bit and one of a plurality of radially distributed strobe signals, and is configured to register the state of the one of the successively delayed versions of the data bit upon assertion of the one of a plurality of radially distributed strobe signals.

Abstract translation: 提供了一种补偿同步数据总线上的未对准的装置。 该装置包括复制径向分布元件，位延迟控制元件和同步延迟接收器，其被配置为接收多个径向分布的选通中的一个和数据位，并且被配置为延迟数据位的寄存 传播时间。 复制径向分布元件被配置为接收第一信号，并且被配置为生成第二信号，其中副本径向分布元件包括用于选通脉冲的径向分布网络的复制传播路径长度，负载和缓冲。 比特滞后控制元件被配置为测量从第一信号的断言开始并以第二信号的断言结束的传播时间，并且被配置为在指示传播时间的滞后总线上生成值。 同步延迟接收器具有第一多个匹配的反相器，第一复用器和位接收器。 第一多个匹配的反相器被配置为产生数据位的连续延迟版本。 第一复用器耦合到第一多个匹配的反相器，并且被配置为在延迟总线上接收指示传播时间的值，并且被配置为选择对应于该值的数据位的连续延迟版本中的一个 。 位接收器被配置为接收数据位的连续延迟版本中的一个和多个径向分布的选通信号中的一个，并且被配置为在断言时注册数据位的连续延迟版本中的一个的状态 的多个径向分布的选通信号中的一个。

公开(公告)号：US09552321B2

公开(公告)日：2017-01-24

申请号：US13757480

申请日：2013-02-01

Applicant: VIA Technologies, Inc.

Inventor： Vanessa S. Canac ,  James R. Lundberg

IPC: G06F13/42

CPC classification number: G06F13/4243 ,  G06F1/12 ,  G06F13/4217 ,  G11C7/1072 ,  G11C8/18

Abstract: A method for aligning signals on a bus, including: replicating propagation path lengths, loads, and buffering of a radial distribution network for a strobe; receiving a first signal, and generating a second signal by employing the replicated propagation path lengths, loads, and buffering; receiving control information over a standard JTAG bus, wherein the control information indicates an amount to adjust a propagation time; and measuring the propagation time beginning with assertion of the first signal and ending with assertion of the second signal, said measuring comprising: selecting one of a plurality of successively delayed versions of the first signal that coincides with assertion of the second signal; adjusting the propagation time by the amount prescribed by the control information to yield an adjusted propagation time; and gray encoding the adjusted propagation time to generate a value on a lag bus.

Abstract translation: 一种用于在总线上对准信号的方法，包括：复制用于选通的径向分布网络的传播路径长度，负载和缓冲; 接收第一信号，并通过采用复制的传播路径长度，加载和缓冲来产生第二信号; 通过标准JTAG总线接收控制信息，其中所述控制信息指示调整传播时间的量; 并且测量从所述第一信号的断言开始并以所述第二信号的断言结束的所述传播时间，所述测量包括：选择与所述第二信号的断言一致的所述第一信号的多个连续延迟版本中的一个; 将传播时间调整为由控制信息规定的量，以产生经调整的传播时间; 并且对经调整的传播时间灰度编码以在滞后总线上产生一个值。

公开(公告)号：US09450580B2

公开(公告)日：2016-09-20

申请号：US14202313

申请日：2014-03-10

Applicant: VIA TECHNOLOGIES, INC.

Inventor： James R. Lundberg

IPC: G05F1/10 ,  H03K19/00

CPC classification number: H03K19/0008

Abstract: An integrated circuit including a global supply bus, a gated supply bus, a functional circuit coupled to the gated supply bus, a programmable device that stores a programmed control parameter, and a digital power gating system. The digital power gating system includes gating devices and a power gating control system. Each gating device is coupled between the global and gated supply buses and each has a control terminal. The power gating control system controls a digital control value to control activation of the gating devices. The power gating control system is configured to perform a power gating operation by adjusting the digital control value to control a voltage of the gated supply bus relative to the voltage of the global supply bus. The power gating operation may be adjusted using the programmed control parameter. The programmable device may be a fuse array or a memory programmed with programmed control parameter.

Abstract translation: 包括全局电源总线，门控电源总线，耦合到门控电源总线的功能电路，存储编程控制参数的可编程器件和数字电源门控系统的集成电路。 数字电源门控系统包括门控设备和电源门控控制系统。 每个选通装置耦合在全局和门控供电总线之间，并且每个具有控制终端。 电源门控控制系统控制数字控制值以控制门控设备的激活。 电源门控控制系统被配置为通过调整数字控制值来执行电力门控操作，以控制门控电源总线相对于全局电源总线的电压的电压。 电源门控操作可以使用编程的控制参数进行调整。 可编程器件可以是保险丝阵列或用编程控制参数编程的存储器。