公开(公告)号：US20140013058A1

公开(公告)日：2014-01-09

申请号：US13872527

申请日：2013-04-29

Applicant: VIA Technologies, Inc.

Inventor： Rodney E. Hooker ,  Colin Eddy

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/10 ,  G06F2212/6028

Abstract: A microprocessor includes a translation lookaside buffer, a request to load a page table entry into the microprocessor generated in response to a miss of a virtual address in the translation lookaside buffer, and a prefetch unit. The prefetch unit receives a physical address of a first cache line that includes the requested page table entry and responsively generates a request to prefetch into the microprocessor a second cache line that is the next physically sequential cache line to the first cache line.

Abstract translation: 微处理器包括翻译后备缓冲器，将页表条目加载到微处理器中的请求，该请求响应于翻译后备缓冲器中的虚拟地址的错过而产生，以及预取单元。 预取单元接收包括所请求的页表条目的第一高速缓存行的物理地址，并且响应地生成将第二高速缓存行预取到微处理器的请求，该第二高速缓存行是到第一高速缓存行的下一物理连续高速缓存行。

公开(公告)号：US20150089204A1

公开(公告)日：2015-03-26

申请号：US14050687

申请日：2013-10-10

Applicant: VIA Technologies, Inc.

Inventor： G. Glenn Henry ,  Rodney E. Hooker ,  Colin Eddy ,  Terry Parks

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G06F8/654 ,  G06F9/30181 ,  G06F15/7892 ,  G06F17/5054

Abstract: A microprocessor includes a plurality of dynamically reconfigurable functional units, a fingerprint, and a fingerprint unit. As the plurality of dynamically reconfigurable functional units execute instructions according to a first configuration setting, the fingerprint unit accumulates information about the instructions according to a mathematical operation to generate a result. The microprocessor also includes a reconfiguration unit that reconfigures the plurality of dynamically reconfigurable functional units to execute instructions according to a second configuration setting in response to an indication that the result matches the fingerprint.

Abstract translation: 微处理器包括多个动态可重构功能单元，指纹和指纹单元。 当多个动态可重构功能单元根据第一配置设置执行指令时，指纹单元根据数学运算累加关于指令的信息以产生结果。 微处理器还包括重配置单元，其重新配置多个动态可重配置功能单元，以响应于结果与指纹匹配的指示，根据第二配置设置来执行指令。

公开(公告)号：US09569363B2

公开(公告)日：2017-02-14

申请号：US14790467

申请日：2015-07-02

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Rodney E. Hooker ,  Colin Eddy

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/0862 ,  G06F12/10 ,  G06F12/1027 ,  G06F2212/1024 ,  G06F2212/251 ,  G06F2212/6022 ,  G06F2212/6028 ,  G06F2212/684 ,  G06F2212/654

Abstract: A microprocessor includes a translation lookaside buffer and a first request to load into the microprocessor a page table entry in response to a miss of a virtual address in the translation lookaside buffer. The requested page table entry is included in a page table. The page table encompasses a plurality of cache lines including a first cache line that includes the requested page table entry. The microprocessor also includes hardware logic that makes a determination whether a second cache line physically sequential to the first cache line is outside the page table, and a second request to prefetch the second cache line into the microprocessor. The second request is selectively generated based at least on the determination made by the hardware logic.

Abstract translation: 微处理器包括翻译后备缓冲器和响应于翻译后备缓冲器中的虚拟地址的缺失而将微处理器加载到页表条目的第一请求。 请求的页表项包含在页表中。 该页表包含多条高速缓存行，包括包含所请求的页表项的第一高速缓存行。 微处理器还包括硬件逻辑，其确定与第一高速缓存行物理连续的第二高速缓存线是否在页表之外，以及将第二高速缓存线预取到微处理器中的第二请求。 至少基于硬件逻辑的判定来选择性地生成第二请求。