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    Processor that recovers from excessive approximate computing error
    1.
    发明授权
    Processor that recovers from excessive approximate computing error 有权
    处理器从过大的近似计算错误中恢复

    公开(公告)号：US09588845B2

    公开(公告)日：2017-03-07

    申请号：US14522520

    申请日：2014-10-23

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker

    IPC: G06F11/14 ,  G06F11/07 ,  G06F9/38

    CPC classification number: G06F11/1446 ,  G06F9/30014 ,  G06F9/30185 ,  G06F9/38 ,  G06F9/3863 ,  G06F11/0754 ,  G06F11/0793 ,  G06F11/1402 ,  G06F11/1435 ,  G06F2201/84

    Abstract: A processor includes a storage configured to receive a snapshot of a state of the processor prior to performing a set of computations in an approximating manner. The processor also includes an indicator that indicates an amount of error accumulated while the set of computations is performed in the approximating manner. When the processor detects that the amount of error accumulated has exceeded an error bound, the processor is configured to restore the state of the processor to the snapshot from the storage.

    Abstract translation: 处理器包括被配置为在以近似方式执行一组计算之前接收处理器的状态的快照的存储器。 处理器还包括指示器，其指示在以近似方式执行计算集合时累积的误差量。 当处理器检测到累积的错误量超过了错误限制时，处理器被配置为将处理器的状态从存储恢复到快照。

    Selective accumulation and use of predicting unit history
    2.
    发明授权
    Selective accumulation and use of predicting unit history 有权
    选择性积累和使用预测单位历史

    公开(公告)号：US09507597B2

    公开(公告)日：2016-11-29

    申请号：US14165354

    申请日：2014-01-27

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： Rodney E. Hooker ,  Terry Parks ,  John Michael Greer

    IPC: G06F9/00 ,  G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/30058 ,  G06F9/3848 ,  G06F9/3851

    Abstract: A microprocessor includes a predicting unit and a control unit. The control unit controls the predicting unit to accumulate a history of characteristics of executed instructions and makes predictions related to subsequent instructions based on the history while the microprocessor is running a first thread. The control unit also detects a transition from running the first thread to running a second thread and controls the predicting unit to selectively suspend accumulating the history and making the predictions using the history while running the second thread. The predicting unit makes static predictions while running the second thread. The selectivity may be based on the privilege level, identity or length of the second thread, static prediction effectiveness during a previous execution instance of the thread, whether the transition was made due to a system call, and whether the second thread is an interrupt handler.

    Abstract translation: 微处理器包括预测单元和控制单元。 控制单元控制预测单元累积执行指令的特征历史，并且在微处理器运行第一线程的同时基于历史来进行与后续指令相关的预测。 控制单元还检测从运行第一线程到运行第二线程的转变，并且控制预测单元选择性地暂停累积历史并且在运行第二线程时使用历史进行预测。 预测单元在运行第二个线程时进行静态预测。 选择性可以基于第二线程的特权级别，身份或长度，线程的先前执行实例期间的静态预测有效性，是否由于系统调用而进行转换，以及第二线程是否是中断处理程序 。

    SELECTIVE ACCUMULATION AND USE OF PREDICTING UNIT HISTORY
    3.
    发明申请
    SELECTIVE ACCUMULATION AND USE OF PREDICTING UNIT HISTORY 有权
    选择性累积和预测单位历史的使用

    公开(公告)号：US20140365753A1

    公开(公告)日：2014-12-11

    申请号：US14165354

    申请日：2014-01-27

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： Rodney E. Hooker ,  Terry Parks ,  John Michael Greer

    IPC: G06F9/30

    CPC classification number: G06F9/30058 ,  G06F9/3848 ,  G06F9/3851

    Abstract: A microprocessor includes a predicting unit and a control unit. The control unit controls the predicting unit to accumulate a history of characteristics of executed instructions and makes predictions related to subsequent instructions based on the history while the microprocessor is running a first thread. The control unit also detects a transition from running the first thread to running a second thread and controls the predicting unit to selectively suspend accumulating the history and making the predictions using the history while running the second thread. The predicting unit makes static predictions while running the second thread. The selectivity may be based on the privilege level, identity or length of the second thread, static prediction effectiveness during a previous execution instance of the thread, whether the transition was made due to a system call, and whether the second thread is an interrupt handler.

    Abstract translation: 微处理器包括预测单元和控制单元。 控制单元控制预测单元累积执行指令的特征历史，并且在微处理器运行第一线程的同时基于历史来进行与后续指令相关的预测。 控制单元还检测从运行第一线程到运行第二线程的转变，并且控制预测单元选择性地暂停累积历史并且在运行第二线程时使用历史进行预测。 预测单元在运行第二个线程时进行静态预测。 选择性可以基于第二线程的特权级别，身份或长度，线程的先前执行实例期间的静态预测有效性，是否由于系统调用而进行转换，以及第二线程是否是中断处理程序 。

    DEADLOCK/LIVELOCK RESOLUTION USING SERVICE PROCESSOR
    4.
    发明申请
    DEADLOCK/LIVELOCK RESOLUTION USING SERVICE PROCESSOR 有权
    使用服务处理器的死锁/潜水解决方案

    公开(公告)号：US20130318530A1

    公开(公告)日：2013-11-28

    申请号：US13758924

    申请日：2013-02-04

    Applicant: VIA Technologies, Inc.

    Inventor： Rodney E. Hooker

    IPC: G06F9/52

    CPC classification number: G06F9/526 ,  G06F9/38 ,  G06F9/3836 ,  G06F11/0721 ,  G06F11/0751 ,  G06F11/0793

    Abstract: A microprocessor includes a main processor and a service processor. The service processor is configured to detect and break a deadlock/livelock condition in the main processor. The service processor detects the deadlock/livelock condition by detecting the main processor has not retired an instruction or completed a processor bus transaction for a predetermined number of clock cycles. In response to detecting the deadlock/livelock condition in the main processor, the service processor causes arbitration requests to a cache memory to be captured in a buffer, analyzes the captured requests to detect a pattern that may indicate a bug causing the condition and performs actions associated with the pattern to break the deadlock/livelock. The actions include suppression of arbitration requests to the cache, suppression of comparisons cache request addresses and killing requests to access the cache.

    Abstract translation: 微处理器包括主处理器和服务处理器。 服务处理器被配置为检测并破坏主处理器中的死锁/活动锁定状态。 服务处理器通过检测主处理器未停止指令或完成处理器总线事务达预定数量的时钟周期来检测死锁/活动锁定状况。 响应于检测到主处理器中的死锁/活动锁定状况，服务处理器将向高速缓冲存储器提出仲裁请求以在缓冲器中被捕获，分析所捕获的请求以检测可能指示导致条件的错误并执行动作的模式 与模式相关联以打破僵局/活锁。 这些操作包括抑制对缓存的仲裁请求，抑制比较缓存请求地址和杀死访问高速缓存的请求。

    Dynamically updating hardware prefetch trait to exclusive or shared at program detection
    5.
    发明授权
    Dynamically updating hardware prefetch trait to exclusive or shared at program detection 有权

    公开(公告)号：US10514920B2

    公开(公告)日：2019-12-24

    申请号：US14625124

    申请日：2015-02-18

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： Rodney E. Hooker ,  Albert J. Loper ,  John Michael Greer

    IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0842 ,  G06F12/0831 ,  G06F3/06 ,  G06F12/0862 ,  G06F12/084

    Abstract: A processor includes a processing core that detects a predetermined program is running on the processor and looks up a prefetch trait associated with the predetermined program running on the processor, wherein the prefetch trait is either exclusive or shared. The processor also includes a hardware data prefetcher that performs hardware prefetches for the predetermined program using the prefetch trait. Alternatively, the processing core loads each of one or more range registers of the processor with a respective address range in response to detecting that the predetermined program is running on the processor. Each of the one or more address ranges has an associated prefetch trait, wherein the prefetch trait is either exclusive or shared. The hardware data prefetcher performs hardware prefetches for the predetermined program using the prefetch traits associated with the address ranges loaded into the range registers.

    Asymmetric multi-core processor with native switching mechanism
    6.
    发明授权
    Asymmetric multi-core processor with native switching mechanism 有权

    公开(公告)号：US10423216B2

    公开(公告)日：2019-09-24

    申请号：US14077740

    申请日：2013-11-12

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： Rodney E. Hooker ,  Terry Parks ,  G. Glenn Henry

    IPC: G06F9/46 ,  G06F1/3293 ,  G06F9/50

    Abstract: A processor includes first and second processing cores configured to support first and second respective subsets of features of its instruction set architecture (ISA) feature set. The first subset is less than all the features of the ISA feature set. The first and second subsets are different but their union is all the features of the ISA feature set. The first core detects a thread, while being executed by the first core rather than by the second core, attempted to employ a feature not in the first subset and, in response, to indicate a switch from the first core to the second core to execute the thread. The unsupported feature may be an unsupported instruction or operating mode. A switch may also be made if the lower performance/power core is being over-utilized or the higher performance/power core is being under-utilized.

    ASYMMETRIC MULTI-CORE PROCESSOR WITH NATIVE SWITCHING MECHANISM
    8.
    发明申请
    ASYMMETRIC MULTI-CORE PROCESSOR WITH NATIVE SWITCHING MECHANISM 有权
    不对称多核心处理器与本地切换机制

    公开(公告)号：US20140298060A1

    公开(公告)日：2014-10-02

    申请号：US14077740

    申请日：2013-11-12

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： Rodney E. Hooker ,  Terry Parks ,  G. Glenn Henry

    IPC: G06F1/32

    Abstract: A processor includes first and second processing cores configured to support first and second respective subsets of features of its instruction set architecture (ISA) feature set. The first subset is less than all the features of the ISA feature set. The first and second subsets are different but their union is all the features of the ISA feature set. The first core detects a thread, while being executed by the first core rather than by the second core, attempted to employ a feature not in the first subset and, in response, to indicate a switch from the first core to the second core to execute the thread. The unsupported feature may be an unsupported instruction or operating mode. A switch may also be made if the lower performance/power core is being over-utilized or the higher performance/power core is being under-utilized.

    Abstract translation: 处理器包括被配置为支持其指令集体系结构（ISA）特征集的特征的第一和第二相应子集的第一和第二处理核心。 第一个子集小于ISA功能集的所有功能。 第一个和第二个子集是不同的，但它们的联合是ISA功能集的所有功能。 第一核心在由第一核心而不是第二核心执行的同时检测线程，尝试使用不在第一子集中的特征，并且响应地指示从第一核到第二核的切换以执行 线程。 不支持的功能可能是不支持的指令或操作模式。 如果较低性能/功率核心被过度利用或较高性能/功率核心利用不足，也可能产生开关。

    PREFETCHING OF NEXT PHYSICALLY SEQUENTIAL CACHE LINE AFTER CACHE LINE THAT INCLUDES LOADED PAGE TABLE ENTRY
    9.
    发明申请
    PREFETCHING OF NEXT PHYSICALLY SEQUENTIAL CACHE LINE AFTER CACHE LINE THAT INCLUDES LOADED PAGE TABLE ENTRY 审中-公开
    高速缓存行后面的下一个物理连续缓存行的预置，其中包括加载页表输入

    公开(公告)号：US20140013058A1

    公开(公告)日：2014-01-09

    申请号：US13872527

    申请日：2013-04-29

    Applicant: VIA Technologies, Inc.

    Inventor： Rodney E. Hooker ,  Colin Eddy

    IPC: G06F12/08

    CPC classification number: G06F12/0862 ,  G06F12/10 ,  G06F2212/6028

    Abstract: A microprocessor includes a translation lookaside buffer, a request to load a page table entry into the microprocessor generated in response to a miss of a virtual address in the translation lookaside buffer, and a prefetch unit. The prefetch unit receives a physical address of a first cache line that includes the requested page table entry and responsively generates a request to prefetch into the microprocessor a second cache line that is the next physically sequential cache line to the first cache line.

    Abstract translation: 微处理器包括翻译后备缓冲器，将页表条目加载到微处理器中的请求，该请求响应于翻译后备缓冲器中的虚拟地址的错过而产生，以及预取单元。 预取单元接收包括所请求的页表条目的第一高速缓存行的物理地址，并且响应地生成将第二高速缓存行预取到微处理器的请求，该第二高速缓存行是到第一高速缓存行的下一物理连续高速缓存行。

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