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    Method and transceiver system having a transmit clock signal phase that is phase-locked with a receive clock signal phase
    1.
    发明授权
    Method and transceiver system having a transmit clock signal phase that is phase-locked with a receive clock signal phase 有权
    方法和收发机系统具有与接收时钟信号相锁相的发射时钟信号相位

    公开(公告)号：US08111738B2

    公开(公告)日：2012-02-07

    申请号：US12881108

    申请日：2010-09-13

    Applicant: Abbas Amirichimeh ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

    Inventor： Abbas Amirichimeh ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

    IPC: H04B1/38 ,  H04L7/00 ,  H04L23/00

    CPC classification number: H03K5/135 ,  H04L7/0012 ,  H04L7/0091

    Abstract: A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.

    Abstract translation: 公开了一种收发器系统，其包括多个收发器芯片。 每个收发器芯片包括一个或多个SERDES内核。 每个SERDES核心包​​括一个或多个SERDES通道。 每个SERDES通道包括接收通道和发送通道。 每个SERDES通道的发送通道与相应的接收通道锁相。 收发器系统具有将发送部件的发送时钟信号相位锁定在接收部件的接收时钟信号相位的能力，该接收时钟信号相位是不同SERDES通道的一部分的接收时钟信号相位，不同的SERDES内核，不同的基板，甚至是 一个不同的董事会。 每个SERDES核心接收和传输连接到SERDES核心的外部组件（例如硬盘驱动器）的数据。 还公开了将数据从耦合到接收信道的第一外部组件传送到耦合到发射信道的第二外部组件的方法。

    Transceiver system and method having a transmit clock signal phase that is phase-locked with a receive clock signal phase
    2.
    发明授权
    Transceiver system and method having a transmit clock signal phase that is phase-locked with a receive clock signal phase 有权
    收发器系统和方法具有与接收时钟信号相位锁相的发射时钟信号相位

    公开(公告)号：US07593457B2

    公开(公告)日：2009-09-22

    申请号：US10813363

    申请日：2004-03-31

    Applicant: Abbas Amirichimeh ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

    Inventor： Abbas Amirichimeh ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

    IPC: H04B1/38 ,  H04L7/00

    CPC classification number: H03K5/135 ,  H04L7/0012 ,  H04L7/0091

    Abstract: A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.

    Abstract translation: 公开了一种收发器系统，其包括多个收发器芯片。 每个收发器芯片包括一个或多个SERDES内核。 每个SERDES核心包​​括一个或多个SERDES通道。 每个SERDES通道包括接收通道和发送通道。 每个SERDES通道的发送通道与相应的接收通道锁相。 收发器系统具有将发送部件的发送时钟信号相位锁定在接收部件的接收时钟信号相位的能力，该接收时钟信号相位是不同SERDES通道的一部分的接收时钟信号相位，不同的SERDES内核，不同的基板，甚至是 一个不同的董事会。 每个SERDES核心接收和传输连接到SERDES核心的外部组件（例如硬盘驱动器）的数据。 还公开了将数据从耦合到接收信道的第一外部组件传送到耦合到发射信道的第二外部组件的方法。

    Method of monitoring the quality of a communications channel
    4.
    发明申请
    Method of monitoring the quality of a communications channel 有权
    监控通信信道质量的方法

    公开(公告)号：US20050188284A1

    公开(公告)日：2005-08-25

    申请号：US10767729

    申请日：2004-01-30

    Applicant: Jay Proano ,  Howard Baumer ,  Chung-Jue Chen ,  Ali Ghiasi ,  Vasudevan Parthasarathy ,  Rajesh Satapathy ,  Linda Ying

    Inventor： Jay Proano ,  Howard Baumer ,  Chung-Jue Chen ,  Ali Ghiasi ,  Vasudevan Parthasarathy ,  Rajesh Satapathy ,  Linda Ying

    IPC: G06F11/00

    CPC classification number: H04L43/022 ,  H04L43/0811 ,  H04L43/0823 ,  H04L43/16

    Abstract: A method is presented that monitors the quality of a communications channel. The method includes receiving a data signal and establishing a zero reference phase of the received data signal. The method further includes generating a phase-shifted data signal by phase shifting the received data signal relative to the zero reference phase, and sampling the phase-shifted data signal for one or more phase-shift positions. A zero reference phase is reestablished between sampling at each of the phase-shift positions. The method also includes detecting bit errors in the phase-shifted data signal at each of the phase-shift positions in order to provide a communications channel quality measurement. In an embodiment, the method includes generating an eye diagram according to a count of detected bit errors relative to a count of detected bits. The eye diagram characterizes the quality of the communications channel.

    Abstract translation: 提出了一种监测通信信道质量的方法。 该方法包括接收数据信号并建立接收数据信号的零参考相位。 该方法还包括通过相对于零参考相位相移所接收的数据信号来产生相移数据信号，并对一个或多个相移位置的相移数据信号进行采样。 在每个相移位置的采样之间重新建立零参考相位。 该方法还包括检测每个相移位置处的相移数据信号中的位错误，以提供通信信道质量测量。 在一个实施例中，该方法包括根据检测到的比特错误的计数相对于检测到的比特的计数来生成眼图。 眼图描绘了通信信道的质量。

    Apparatus and method for automatic polarity swap in a communications system
    5.
    发明申请
    Apparatus and method for automatic polarity swap in a communications system 有权
    通信系统中自动极性交换的装置和方法

    公开(公告)号：US20050094734A1

    公开(公告)日：2005-05-05

    申请号：US10694945

    申请日：2003-10-29

    Applicant: Vasudevan Parthasarathy

    Inventor： Vasudevan Parthasarathy

    IPC: H04B3/00

    CPC classification number: H04L25/0272 ,  H04L25/02 ,  H04L25/0292

    Abstract: An automatic polarity swap is implemented in a communications system. Two or more transceivers having differential inputs and outputs are coupled together through an interface, such as a backplane to form a communications system. In such a configuration, it is possible to cross-connect the differential data lines or signals at the interface, which will cause invalid data words to received at the second transceiver. Accordingly, the present invention includes an error check and correction module that detects invalid data words after parallel-to-serial conversion. More specifically, an error check determines if the parallel differential signal represents a valid data word. This can be done, for example, by storing and comparing valid data words in a memory such as RAM. If the received data word is valid, then no corrective action is taken. However, if the received data word is invalid, then the parallel differential signal is inverted using a logic circuit, which will correct the error if it is due to cross-connection of the differential lines at the interface or anywhere else.

    Abstract translation: 在通信系统中实现自动极性交换。 具有差分输入和输出的两个或多个收发器通过诸如背板的接口耦合在一起以形成通信系统。 在这种配置中，可以将接口处的差分数据线或信号交叉连接，这将导致在第二收发器处接收的无效数据字。 因此，本发明包括在并行到串行转换之后检测无效数据字的错误检查和校正模块。 更具体地，错误检查确定并行差分信号是否表示有效的数据字。 这可以通过例如存储和比较诸如RAM的存储器中的有效数据字来完成。 如果接收到的数据字有效，则不采取任何纠正措施。 然而，如果接收到的数据字无效，则使用逻辑电路对并行差分信号进行反相，如果由于差分线在接口或其他任何地方的交叉连接，则将纠正错误。

    Systems for high-speed backplane applications using pre-coding
    6.
    发明授权
    Systems for high-speed backplane applications using pre-coding 失效
    使用预编码的高速底板应用系统

    公开(公告)号：US08661309B2

    公开(公告)日：2014-02-25

    申请号：US13014519

    申请日：2011-01-26

    Applicant: William Bliss ,  Vasudevan Parthasarathy

    Inventor： William Bliss ,  Vasudevan Parthasarathy

    IPC: H03M13/00

    CPC classification number: H03M13/151 ,  H03M13/05 ,  H03M13/1515 ,  H04B7/0456 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0057 ,  H04L25/03949 ,  H04L25/4917 ,  H04L27/00 ,  H04L27/02

    Abstract: In conventional Backplane Ethernet systems, data is transmitted over two pairs of copper traces in one direction using a PAM-2 scheme and a baud rate of 10.3125 GHz, giving an effective bit rate of 10.3125 Gbps. The rate at which data can be transmitted in Backplane Ethernet systems, while still being reliably received, is typically limited by ISI caused by the dispersive nature of the copper traces, frequency dependent transmission losses caused primarily by skin effect and dielectric loss of the copper traces, and cross-talk from adjacent communication lines. The present invention is directed to systems for overcoming these and other signal impairments to achieve speeds up to, and beyond, twice the conventional 10 Gbps limit associated with Backplane Ethernet systems.

    Abstract translation: 在传统的背板以太网系统中，使用PAM-2方案和10.3125 GHz的波特率，通过两对铜线路在一个方向上传输数据，提供10.3125 Gbps的有效比特率。 在背板以太网系统中数据传输的速率仍然可靠地接收，通常受到铜迹线色散性质引起的ISI的限制，主要由皮肤效应引起的频率依赖传输损耗和铜迹线的介电损耗 ，以及相邻通信线路的串扰。 本发明涉及用于克服这些和其他信号损伤的系统，以实现高达和超过与背板以太网系统相关联的常规10Gbps限制的两倍的速度。

    Method and Transceiver System Having a Transmit Clock Signal Phase that is Phase-Locked with a Receive Clock Signal Phase
    7.
    发明申请
    Method and Transceiver System Having a Transmit Clock Signal Phase that is Phase-Locked with a Receive Clock Signal Phase 有权
    具有与接收时钟信号相锁相的发送时钟信号相位的方法和收发器系统

    公开(公告)号：US20120201280A1

    公开(公告)日：2012-08-09

    申请号：US13367282

    申请日：2012-02-06

    Applicant: Abbas AMIRICHIMEH ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

    Inventor： Abbas AMIRICHIMEH ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

    IPC: H04B1/38

    CPC classification number: H03K5/135 ,  H04L7/0012 ,  H04L7/0091

    Abstract: A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.

    Abstract translation: 公开了一种收发器系统，其包括多个收发器芯片。 每个收发器芯片包括一个或多个SERDES内核。 每个SERDES核心包​​括一个或多个SERDES通道。 每个SERDES通道包括接收通道和发送通道。 每个SERDES通道的发送通道与相应的接收通道锁相。 收发器系统具有将发送部件的发送时钟信号相位锁定在接收部件的接收时钟信号相位的能力，该接收时钟信号相位是不同SERDES通道的一部分的接收时钟信号相位，不同的SERDES内核，不同的基板，甚至是 一个不同的董事会。 每个SERDES核心接收和传输连接到SERDES核心的外部组件（例如硬盘驱动器）的数据。 还公开了将数据从耦合到接收信道的第一外部组件传送到耦合到发射信道的第二外部组件的方法。

    Method and Transceiver System Having a Transmit Clock Signal Phase that is Phase-Locked with a Receive Clock Signal Phase
    8.
    发明申请
    Method and Transceiver System Having a Transmit Clock Signal Phase that is Phase-Locked with a Receive Clock Signal Phase 有权
    具有与接收时钟信号相锁相的发送时钟信号相位的方法和收发器系统

    公开(公告)号：US20090232192A1

    公开(公告)日：2009-09-17

    申请号：US12476207

    申请日：2009-06-01

    Applicant: Abbas AMIRICHIMEH ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

    Inventor： Abbas AMIRICHIMEH ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

    IPC: H04B1/38

    CPC classification number: H03K5/135 ,  H04L7/0012 ,  H04L7/0091

    Abstract: A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.

    Abstract translation: 公开了一种收发器系统，其包括多个收发器芯片。 每个收发器芯片包括一个或多个SERDES内核。 每个SERDES核心包​​括一个或多个SERDES通道。 每个SERDES通道包括接收通道和发送通道。 每个SERDES通道的发送通道与相应的接收通道锁相。 收发器系统具有将发送部件的发送时钟信号相位锁定在接收部件的接收时钟信号相位的能力，该接收时钟信号相位是不同SERDES通道的一部分的接收时钟信号相位，不同的SERDES内核，不同的基板，甚至是 一个不同的董事会。 每个SERDES核心接收和传输连接到SERDES核心的外部组件（例如硬盘驱动器）的数据。 还公开了将数据从耦合到接收信道的第一外部组件传送到耦合到发射信道的第二外部组件的方法。

    System for monitoring the quality of a communications channel with mirror receivers
    9.
    发明申请
    System for monitoring the quality of a communications channel with mirror receivers 有权
    用镜像接收机监控通信通道质量的系统

    公开(公告)号：US20080212665A1

    公开(公告)日：2008-09-04

    申请号：US12071138

    申请日：2008-02-15

    Applicant: Jay Proano ,  Howard Baumer ,  Chung-Jue Chen ,  Ali Ghiasi ,  Vasudevan Parthasarathy ,  Rajesh Satapathy ,  Linda Ying

    Inventor： Jay Proano ,  Howard Baumer ,  Chung-Jue Chen ,  Ali Ghiasi ,  Vasudevan Parthasarathy ,  Rajesh Satapathy ,  Linda Ying

    IPC: H04B3/46 ,  H04B17/00

    CPC classification number: H04L43/0823

    Abstract: A system is presented that monitors the quality of a communications channel with mirror receivers. A first receiver and a second receiver, coupled in parallel with the first receiver, receive a data signal transmitted over the communications channel. The second receiver generates an output signal. A signal integrity (SI) processor manipulates the output signal in order to determine the quality of the communications channel. The SI processor samples a phase-shifted version of the output signal, which has a phase shifted relative to a zero reference phase, and analyzes the phase-shifted version of the output signal for bit errors. In an embodiment, the SI processor manipulates the output signal to extract an eye diagram indicative of the quality of the communications channel. The SI processor non-intrusively determines the quality of the communications channel using the second receiver.

    Abstract translation: 提出了一种监控带有镜像接收器的通信通道质量的系统。 与第一接收机并联耦合的第一接收机和第二接收机接收通过通信信道发送的数据信号。 第二个接收器产生一个输出信号。 信号完整性（SI）处理器操纵输出信号，以便确定通信信道的质量。 SI处理器对输出信号的相移版本进行采样，该相位版本相对于零参考相位具有相移，并且分析用于位错误的输出信号的相移版本。 在一个实施例中，SI处理器操纵输出信号以提取指示通信信道质量的眼图。 SI处理器非侵入性地确定使用第二接收机的通信信道的质量。

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