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    Techniques for identifying functional blocks in a design that match a template and combining the functional blocks into fewer programmable circuit elements
    1.
    发明授权
    Techniques for identifying functional blocks in a design that match a template and combining the functional blocks into fewer programmable circuit elements 失效
    用于识别与模板匹配并且将功能块组合成更少的可编程电路元件的设计中的功能块的技术

    公开(公告)号：US06957412B1

    公开(公告)日：2005-10-18

    申请号：US10298259

    申请日：2002-11-15

    申请人： Vaughn Betz ,  Elias Ahmed ,  David Neto

    发明人： Vaughn Betz ,  Elias Ahmed ,  David Neto

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054

    摘要： Techniques are provided that combine functional blocks in a user design into fewer programmable circuit elements. Systems and methods of the present invention can combine functional blocks in a user design into a single programmable circuit element. A plurality of functional blocks in a user design that can be combined are identified. The possible combinations of functional blocks can be sorted according to a gain function. The gain function can, for example, weigh routing delays caused by a combination. The most desirable combination is selected from the sorted list of possible combinations. The selected combination is checked to see if it is feasible in light of electrical and user-specified constraints. If the combination is feasible, the combination is performed. Combinations continue to be performed by selecting the most desirable combinations from the sorted list.

    摘要翻译： 提供了将用户设计中的功能块组合成更少的可编程电路元件的技术。 本发明的系统和方法可以将用户设计中的功能块组合成单个可编程电路元件。 识别可以组合的用户设计中的多个功能块。 功能块的可能组合可以根据增益函数进行排序。 增益功能可以例如衡量由组合引起的路由延迟。 最合适的组合是从可能组合的排序列表中选择的。 根据电气和用户指定的限制，检查所选择的组合是否可行。 如果组合可行，则执行组合。 组合继续通过从排序列表中选择最理想的组合来执行。

    Computer-aided-design tools for reducing power consumption in programmable logic devices
    2.
    发明授权
    Computer-aided-design tools for reducing power consumption in programmable logic devices 有权
    用于降低可编程逻辑器件功耗的计算机辅助设计工具

    公开(公告)号：US07555741B1

    公开(公告)日：2009-06-30

    申请号：US11520944

    申请日：2006-09-13

    申请人： David Ian M. Milton ,  David Neto ,  Vaughn Betz

    发明人： David Ian M. Milton ,  David Neto ,  Vaughn Betz

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054 ,  G06F2217/78

    摘要： Methods and apparatus for designing and producing programmable logic devices are provided. A logic design system may be used to analyze various implementations of a desired logic design for a programmable logic device integrated circuit. The logic design system may be used to produce configuration data for the programmable logic device in accordance with an implementation that minimizes power consumption by the programmable logic device. The programmable logic device contains logic blocks that are used to implement the desired logic design and logic blocks that are unused. Dynamic power consumption can be minimized by identifying which configuration data settings reduce the amount of signal toggling in the unused logic blocks and routing, and by minimizing the capacitance of resources that do toggle. Clock tree power consumption can be reduced by evaluating multiple potential logic design implementations using a strictly concave cost function.

    摘要翻译： 提供了设计和制造可编程逻辑器件的方法和设备。 可以使用逻辑设计系统来分析用于可编程逻辑器件集成电路的期望逻辑设计的各种实现。 逻辑设计系统可以用于根据使可编程逻辑器件的功耗最小化的实现来产生可编程逻辑器件的配置数据。 可编程逻辑器件包含用于实现未使用的所需逻辑设计和逻辑块的逻辑块。 可以通过识别哪些配置数据设置减少未使用的逻辑块和路由中的信号切换量以及通过最小化切换的资源的电容来最小化动态功耗。 通过使用严格的凹成本函数评估多个潜在的逻辑设计实现，可以减少时钟树的功耗。

    Power-aware RAM processing
    4.
    发明授权
    Power-aware RAM processing 有权
    电源感知RAM处理

    公开(公告)号：US07877555B1

    公开(公告)日：2011-01-25

    申请号：US11510018

    申请日：2006-08-24

    申请人： Russell George Tessier ,  Vaughn Betz ,  Thiagaraja Golpalsamy ,  David Neto

    发明人： Russell George Tessier ,  Vaughn Betz ,  Thiagaraja Golpalsamy ,  David Neto

    IPC分类号： G06F12/00

    CPC分类号： G11C5/14 ,  G11C7/22 ,  G11C8/12 ,  G11C2207/2227

    摘要： Logical memories and other logic functions specified in designs are mapped to power-optimized implementations using physical memories and other device resources. A logical memory may be automatically mapped to numerous potential physical implementations. Power consumption is estimated for each potential physical implementation to select the physical implementation providing the best performance with respect to power consumption and any other design constraints. Potential physical implementations can suppress clock transitions via clock enable inputs when embedded memory is not accessed. Read-enable and write-enable signals can be converted to functionally equivalent clock enable signals. Clock enable signals can be created to deactivate unused memory access ports and to deactivate embedded memory blocks during don't-care conditions. Potential physical implementations can slice logical memory into two or more embedded memory blocks to minimize power consumption.

    摘要翻译： 逻辑存储器和设计中指定的其他逻辑功能被映射到使用物理存储器和其他设备资源的功率优化实现。 逻辑存储器可以自动映射到许多潜在的物理实现。 对每个潜在的物理实现估计功耗，以选择在功耗和任何其他设计限制方面提供最佳性能的物理实现。 当未访问嵌入式存储器时，潜在的物理实现可以通过时钟使能输入来抑制时钟转换。 读使能和写使能信号可以转换为功能等效的时钟使能信号。 可以创建时钟使能信号，以禁用未使用的存储器访问端口，并在不保养条件期间停用嵌入式存储器块。 潜在的物理实现可以将逻辑存储器分解成两个或多个嵌入式存储器块，以最小化功耗。

    Method and apparatus for protecting, optimizing, and reporting synchronizers
    8.
    发明授权
    Method and apparatus for protecting, optimizing, and reporting synchronizers 有权
    用于保护，优化和报告同步器的方法和装置

    公开(公告)号：US08732639B1

    公开(公告)日：2014-05-20

    申请号：US12384377

    申请日：2009-04-03

    申请人： Ryan Fung ,  Vaughn Betz ,  David Neto

    发明人： Ryan Fung ,  Vaughn Betz ,  David Neto

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5031 ,  G06F17/505 ,  G06F17/5054 ,  G06F2217/84

    摘要： A method for designing a system on a target device using an electronic design automation (EDA) tool including identifying synchronizer chains in a system design using timing relationships. According to one embodiment of the present invention, the method includes conveniently reporting system reliability considering synchronization, and automatically protecting and optimizing synchronizer chains to improve system robustness.

    摘要翻译： 一种使用电子设计自动化（EDA）工具在目标设备上设计系统的方法，包括使用定时关系在系统设计中识别同步器链。 根据本发明的一个实施例，该方法包括方便地报告考虑同步的系统可靠性，并且自动保护和优化同步器链以提高系统的鲁棒性。

    Method and apparatus for implementing cross-talk based booster wires in a system on a field programmable gate array
    9.
    发明授权
    Method and apparatus for implementing cross-talk based booster wires in a system on a field programmable gate array 有权
    用于在现场可编程门阵列上的系统中实现基于串扰的升压线的方法和装置

    公开(公告)号：US08468487B1

    公开(公告)日：2013-06-18

    申请号：US12386739

    申请日：2009-04-22

    申请人： Zahir Parpia ,  Chris Wysocki ,  Vaughn Betz

    发明人： Zahir Parpia ,  Chris Wysocki ,  Vaughn Betz

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054 ,  G06F17/5077

    摘要： A method for designing a system on a field programmable gate array (FPGA) includes routing one or more booster wires alongside an interconnect to reduce a delay of a signal being transmitted on the interconnect. According to one aspect of the present invention, the routing of the one or more booster wires is performed in response to determining that a timing requirement of the system has not been met.

    摘要翻译： 用于在现场可编程门阵列（FPGA）上设计系统的方法包括在互连旁边布置一个或多个升压线，以减少在互连上传输的信号的延迟。 根据本发明的一个方面，响应于确定尚未满足系统的定时要求，执行一个或多个升压线的路由。

    Clock switch-over circuits and methods
    10.
    发明授权
    Clock switch-over circuits and methods 有权
    时钟切换电路和方法

    公开(公告)号：US08248110B1

    公开(公告)日：2012-08-21

    申请号：US13048241

    申请日：2011-03-15

    申请人： Gary Lai ,  Andy L. Lee ,  Ryan Fung ,  Vaughn Betz ,  Marcel A. LeBlanc

    发明人： Gary Lai ,  Andy L. Lee ,  Ryan Fung ,  Vaughn Betz ,  Marcel A. LeBlanc

    IPC分类号： H01H71/22

    CPC分类号： G06F1/10

    摘要： Clock switch-over circuits and methods provide clock signals to clock routing networks. According to one embodiment, a multiplexer selects between a first clock signal and a second clock signal in response to a switch select signal received from a control circuit. A storage circuit stores an enable signal in response to an output clock signal of the multiplexer. A logic circuit transmits the output clock signal of the multiplexer to a clock routing network in response to the enable signal from the storage circuit. At least one signal is transmitted from the clock switch-over circuit to the control circuit.

    摘要翻译： 时钟切换电路和方法为时钟路由网络提供时钟信号。 根据一个实施例，多路复用器响应于从控制电路接收的开关选择信号在第一时钟信号和第二时钟信号之间进行选择。 存储电路响应于多路复用器的输出时钟信号而存储使能信号。 响应于来自存储电路的使能信号，逻辑电路将多路复用器的输出时钟信号传输到时钟路由网络。 至少一个信号从时钟切换电路发送到控制电路。