公开(公告)号：US4168523A

公开(公告)日：1979-09-18

申请号：US858050

申请日：1977-12-06

申请人： Venu Chari ,  Ronald L. Engelbrecht

发明人： Venu Chari ,  Ronald L. Engelbrecht

IPC分类号： G06F9/26 ,  G06F9/20

CPC分类号： G06F9/265

摘要： A data processor utilizes a central processor controller to determine selectively the next required operation phase while executing a current operation phase. Control words contained in a second stage control memory are selectively addressed from addresses contained in a first stage control memory. The selection of a particular address of a control word contained in said first stage control memory is determined from combinations of signals received by a condition multiplexer interposed between said first and second stage control memories, portions of program instructions contained in main memory, externally operated manual switches, and various internal control flags. The operation phase is defined as an operation, which is defined by said control word. The generation of the address for the next required control word and the execution of the operation defined by the current control word occurs in the same machine cycle. Each control word comprises a mode of operation, control signals for the various execute units, and input signals for the condition multiplexer for determining the next operation phase control word address, required by the data processor in the process of executing program instructions contained in the data processor's main memory.

摘要翻译： 数据处理器利用中央处理器控制器在执行当前操作阶段期间选​​择性地确定下一个所需的操作阶段。 包含在第二级控制存储器中的控制字被选择性地从包含在第一级控制存储器中的地址寻址。 包含在所述第一级控制存储器中的控制字的特定地址的选择由插入在所述第一和第二级控制存储器之间的条件复用器接收的信号的组合，主存储器中包含的程序指令的部分，外部操作的手册 开关和各种内部控制标志。 操作阶段被定义为由所述控制字定义的操作。 下一个所需控制字的地址的生成和由当前控制字定义的操作的执行在同一机器周期中发生。 每个控制字包括操作模式，用于各种执行单元的控制信号，以及用于条件多路复用器的输入信号，用于确定数据处理器在执行数据中包含的程序指令的过程中所需的下一个操作相位控制字地址 处理器的主要内存。

公开(公告)号：US4562533A

公开(公告)日：1985-12-31

申请号：US642736

申请日：1984-08-20

申请人： Alfred Hodel ,  Dennis B. Merkes ,  Venu Chari

发明人： Alfred Hodel ,  Dennis B. Merkes ,  Venu Chari

IPC分类号： G06F13/42 ,  G06F15/17

CPC分类号： G06F13/4213 ,  G06F15/17

摘要： This invention relates to an adapter for interprocessor communications and the method therefor. An adapter is included in a data processing system which has a plurality of central systems, each of the plurality of central systems having at least one serial channel control processor. The data processing system further has a dynamic channel exchange for providing switching logic thereby permitting each of the plurality of central systems access to a plurality of peripherals coupled to the dynamic channel exchange. The adapter is operatively connected to the dynamic channel exchange for providing communications between any pair of central systems. The adapter comprises a link control module which provides handshake control to perform message bit/byte synchronization and translation. A message protocol module, which is operatively connected to the link control module, controls the transmission of information with a selected one of the plurality of central systems, the control being administered by interfacing with the serial channel control processor in accordance with a defined message protocol. A data buffer provides intermediate storage of information passed between the pair of central systems. A control processor schedules and monitors the information transfer into and out of the data buffer by interfacing with the message protocol module in accordance with the defined message protocol thereby achieving the information transfer between the pair of central systems.

摘要翻译： 本发明涉及用于处理器间通信的适配器及其方法。 适配器包括在具有多个中央系统的数据处理系统中，多个中央系统中的每一个具有至少一个串行通道控制处理器。 数据处理系统还具有用于提供切换逻辑的动态信道交换，从而允许多个中央系统中的每一个接入耦合到动态信道交换的多个外设。 适配器可操作地连接到动态信道交换机，用于提供任何一对中央系统之间的通信。 适配器包括链路控制模块，其提供用于执行消息比特/字节同步和转换的握手控制。 可操作地连接到链路控制模块的消息协议模块控制与多个中央系统中的所选择的一个中心系统的信息的传输，该控制是通过根据定义的消息协议与串行信道控制处理器接口来管理的 。 数据缓冲器提供在一对中央系统之间传递的信息的中间存储。 控制处理器通过根据定义的消息协议与消息协议模块接口来调度和监视信息传输进出数据缓冲器，从而实现一对中央系统之间的信息传递。

公开(公告)号：US4428046A

公开(公告)日：1984-01-24

申请号：US146805

申请日：1980-05-05

申请人： Venu Chari ,  Jack R. Duke ,  Shimon Gersten

发明人： Venu Chari ,  Jack R. Duke ,  Shimon Gersten

IPC分类号： G06F13/14 ,  G06F15/173 ,  G06F15/16

CPC分类号： G06F15/17337 ,  G06F13/14

摘要： A data processing system having a plurality of subsystems linked by a star coupler. The star coupler includes contention circuitry for controlling the star coupler so that at any given time no more than one selected subsystem can pass a message through the star coupler. The contention circuitry uses a conventional priority encode circuit to determine the selected one of the subsystems, so that the first message to be received from one of the subsystems is the message passed or, if two or more messages are received from subsystems simultaneously, the message from the subsystem having the highest relative priority established by the priority encode circuit is the message passed. In an embodiment showing an expanded star coupler, the contention circuitry has plural first level contention circuits and a second level contention circuit, each using a conventional priority encode circuit.

摘要翻译： 一种具有由星形耦合器连接的多个子系统的数据处理系统。 星形耦合器包括用于控制星形耦合器的争用电路，使得在任何给定时间，不超过一个所选择的子系统可以通过星形耦合器传递消息。 竞争电路使用常规优先级编码电路来确定所选择的一个子系统，使得要从子系统之一接收的第一消息是通过的消息，或者如果从子系统同时接收到两个或更多个消息，消息 来自具有由优先级编码电路建立的最高相对优先级的子系统是通过的消息。 在示出展示的星形耦合器的实施例中，争用电路具有多个第一级争用电路和第二级争用电路，每个使用常规优先级编码电路。

公开(公告)号：US4287596A

公开(公告)日：1981-09-01

申请号：US98019

申请日：1979-11-26

申请人： Venu Chari

发明人： Venu Chari

IPC分类号： H04L27/10 ,  H04L25/49

CPC分类号： H04L25/4904

摘要： A data recovery circuit for use in a data processing system where plural subsystems are linked by a bit serial transmission line. The data transmitted over the bit serial transmission line is in the form of a phase encoded (PE) pulse signal. The data recovery circuit includes a time delay circuit for delaying the PE pulse signal by a three-quarter bit period. The three-quarter bit period delay signal permits the generation of a control clock signal. The control clock signal is used in sampling the PE pulse signal at three-quarter bit period points in order to generate a control signal that indicates the absence or presence of a transition at the midpoint of each bit period of the PE pulse signal. The control signal is used to generate a recovered clock signal by logically combining the control signal with the PE pulse signal and a one-half bit period delayed PE pulse signal. The control signal is also used to generate a recovered data signal by clocking the control signal into two cascaded flip-flops and logically combining the outputs of the two cascaded flip-flops.

摘要翻译： 一种用于数据处理系统的数据恢复电路，其中多个子系统通过位串行传输线链接。 通过位串行传输线传输的数据是相位编码（PE）脉冲信号的形式。 数据恢复电路包括用于将PE脉冲信号延迟四分之三位的时间延迟电路。 三分之三比特周期延迟信号允许产生控制时钟信号。 控制时钟信号用于在三分之四位位周期点对PE脉冲信号进行采样，以产生指示在PE脉冲信号的每个位周期的中点处不存在或不存在转换的控制信号。 控制信号用于通过逻辑地组合控制信号与PE脉冲信号和一个半位周期延迟的PE脉冲信号来产生恢复的时钟信号。 控制信号还用于通过将控制信号计时到两个级联的触发器并逻辑地组合两个级联的触发器的输出来产生恢复的数据信号。