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    Variability resilient sense amplifier with reduced energy consumption
    1.
    发明授权
    Variability resilient sense amplifier with reduced energy consumption 有权
    可变性弹性感应放大器，能耗降低

    公开(公告)号：US08462572B2

    公开(公告)日：2013-06-11

    申请号：US13231706

    申请日：2011-09-13

    申请人： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene ,  Francky Catthoor ,  Maryam Ashouei ,  Jos Huisken

    发明人： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene ,  Francky Catthoor ,  Maryam Ashouei ,  Jos Huisken

    IPC分类号： G11C7/02 ,  G11C7/00 ,  H03F3/45

    CPC分类号： G11C11/413 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08

    摘要： An ultra low power sense amplifier circuit for amplifying a low swing input signal to a full swing output signal is disclosed. In one aspect, the amplifier circuit includes a first amplifier stage for pre-amplifying the input signal to an intermediate signal on its internal nodes, a second amplifier stage for amplifying the intermediate signal to the output signal, and a control circuit for sequentially activating the first and second amplifier. The first amplifier has a capacitor for limiting energy consumption and two upsized PMOS transistors without NMOS transistors.

    摘要翻译： 公开了一种用于将低摆幅输入信号放大到全摆幅输出信号的超低功率读出放大器电路。 在一个方面，放大器电路包括用于将输入信号预放大到其内部节点上的中间信号的第一放大器级，用于将中间信号放大到输出信号的第二放大器级，以及用于依次激活 第一和第二放大器。 第一放大器具有用于限制能量消耗的电容器和没有NMOS晶体管的两个升压PMOS晶体管。

    MEMORY CIRCUIT WITH MULTI-SIZED SENSE AMPLIFIER REDUNDANCY
    2.
    发明申请
    MEMORY CIRCUIT WITH MULTI-SIZED SENSE AMPLIFIER REDUNDANCY 审中-公开
    具有多尺寸感应放大器冗余的存储器电路

    公开(公告)号：US20110063934A1

    公开(公告)日：2011-03-17

    申请号：US12879972

    申请日：2010-09-10

    申请人： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene

    发明人： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene

    IPC分类号： G11C7/08

    CPC分类号： G11C29/702 ,  G11C2207/2254

    摘要： A memory circuit with multi-sized sense amplifier redundancy is disclosed. In one aspect, the circuit includes sense amplifiers connected to differential bit-lines and configured to amplify a voltage difference sensed on the differential bit-lines. The sense amplifiers include a first set of smaller sense amplifiers and a second set of larger sense amplifiers redundantly arranged to the first set to form redundant groups which each contain one smaller sense amplifiers and one larger sense amplifiers. The larger sense amplifiers have a failure rate lower than the smaller sense amplifiers. The circuit also includes calibration circuitry connected to enable and disable nodes of each of the sense amplifiers and configured to select for each redundant group either the smaller sense amplifier of the first set or, if the smaller sense amplifier fails, the larger sense amplifier of the second set.

    摘要翻译： 公开了一种具有多尺寸读出放大器冗余的存储器电路。 在一个方面，电路包括连接到差分位线的读出放大器，并被配置为放大在差分位线上感测到的电压差。 读出放大器包括第一组较小读出放大器和第二组较大读出放大器，冗余布置到第一组以形成冗余组，每组包含一个较小的读出放大器和一个较大的读出放大器。 较大的感测放大器的故障率低于较小的感测放大器。 电路还包括校准电路，其连接到启用和禁用每个读出放大器的节点，并且被配置为为每个冗余组选择第一组的较小感测放大器，或者如果较小的读出放大器发生故障，则较大的读出放大器 第二集

    VARIABILITY RESILIENT SENSE AMPLIFIER WITH REDUCED ENERGY CONSUMPTION
    3.
    发明申请
    VARIABILITY RESILIENT SENSE AMPLIFIER WITH REDUCED ENERGY CONSUMPTION 有权
    具有降低能源消耗的可变性感应放大器

    公开(公告)号：US20120063252A1

    公开(公告)日：2012-03-15

    申请号：US13231706

    申请日：2011-09-13

    申请人： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene ,  Francky Catthoor ,  Maryam Ashouei ,  Jos Huisken

    发明人： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene ,  Francky Catthoor ,  Maryam Ashouei ,  Jos Huisken

    IPC分类号： H03F3/45 ,  G11C7/02

    CPC分类号： G11C11/413 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08

    摘要： An ultra low power sense amplifier circuit for amplifying a low swing input signal to a full swing output signal is disclosed. In one aspect, the amplifier circuit includes a first amplifier stage for pre-amplifying the input signal to an intermediate signal on its internal nodes, a second amplifier stage for amplifying the intermediate signal to the output signal, and a control circuit for sequentially activating the first and second amplifier. The first amplifier has a capacitor for limiting energy consumption and two upsized PMOS transistors without NMOS transistors.

    摘要翻译： 公开了一种用于将低摆幅输入信号放大到全摆幅输出信号的超低功率读出放大器电路。 在一个方面，放大器电路包括用于将输入信号预放大到其内部节点上的中间信号的第一放大器级，用于将中间信号放大到输出信号的第二放大器级，以及用于依次激活 第一和第二放大器。 第一放大器具有用于限制能量消耗的电容器和没有NMOS晶体管的两个升压PMOS晶体管。

    METHOD FOR IMPROVING WRITABILITY OF SRAM MEMORY
    4.
    发明申请
    METHOD FOR IMPROVING WRITABILITY OF SRAM MEMORY 审中-公开
    改进SRAM存储器可写性的方法

    公开(公告)号：US20120063211A1

    公开(公告)日：2012-03-15

    申请号：US13231727

    申请日：2011-09-13

    申请人： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene ,  Francky Catthoor ,  Maryan Ashouei ,  Jos Huisken

    发明人： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene ,  Francky Catthoor ,  Maryan Ashouei ,  Jos Huisken

    IPC分类号： G11C11/00

    CPC分类号： G11C11/413 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08

    摘要： A method for improving writability of an SRAM cell is disclosed. In one aspect, the method includes applying a first voltage higher than the global ground voltage and a third voltage higher than the global supply voltage to the ground supply nodes of the invertors of the SRAM cell, pre-charging one of the complementary bitlines to the global ground voltage, and applying a second voltage higher than the global supply voltage to the access transistors during a write operation to the SRAM cell.

    摘要翻译： 公开了一种提高SRAM单元可写性的方法。 一方面，该方法包括将高于全局接地电压的第一电压和高于全局电源电压的第三电压施加到SRAM单元的反相器的接地电源节点，将互补位线之一预充电至 全局接地电压，并且在对SRAM单元的写入操作期间将高于全局电源电压的第二电压施加到存取晶体管。

    HIERARCHICAL BUFFERED SEGMENTED BIT-LINES BASED SRAM
    5.
    发明申请
    HIERARCHICAL BUFFERED SEGMENTED BIT-LINES BASED SRAM 审中-公开
    基于分层缓存的基于位线的SRAM

    公开(公告)号：US20110305099A1

    公开(公告)日：2011-12-15

    申请号：US13105806

    申请日：2011-05-11

    申请人： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene ,  Francky Catthoor ,  Maryam Ashouei ,  Jos Huisken

    发明人： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene ,  Francky Catthoor ,  Maryam Ashouei ,  Jos Huisken

    IPC分类号： G11C7/12

    CPC分类号： G11C11/419 ,  G11C7/12 ,  G11C7/18 ,  G11C2207/002

    摘要： A semiconductor memory device is disclosed. In one aspect, the device includes memory blocks with memory cells connected to a local bit-line, each local bit-line being connectable to a global bit-line for memory readout. There are also pre-charging circuitry for pre-charging the bit-lines and a read buffer for discharging the global bit-line during a read operation. The local bit-lines are pre-charged to a predetermined first voltage substantially lower than the supply voltage (VDD) of the memory device. A segment buffer is provided between each local bit-line and an input node of the respective read buffer. The segment buffer activates the read buffer during the read operation upon occurrence of a discharge on the connected local bit-line.

    摘要翻译： 公开了一种半导体存储器件。 在一个方面，该设备包括具有连接到本地位线的存储器单元的存储器块，每个局部位线可连接到全局位线用于存储器读出。 还存在用于对位线进行预充电的预充电电路和用于在读操作期间对全局位线进行放电的读缓冲器。 本地位线被预充电到基本上低于存储器件的电源电压（VDD）的预定的第一电压。 在每个本地位线和相应读缓冲器的输入节点之间提供段缓冲器。 在连接的本地位线上发生放电时，段缓冲器在读操作期间激活读缓冲器。