摘要:
Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel diffusions are not suppressed; preferably they have an elevation that is at least as high as that of the diffusion regions.
摘要:
Roughly described, standard SPICE models can be modified by substituting a different stress analyzer to better model the stress adjusted characteristics of a transistor. A first, standard, stress-sensitive, transistor model is used to develop a mathematical relationship between the first transistor performance measure and one or more instance parameters that are available as inputs to a second, stress-insensitive, transistor model. The second transistor model may for example be the same as the first model, with its stress sensitivity disabled. Thereafter, a substitute stress analyzer can be used to determine a stress-adjusted value for the first performance measure, and the mathematical relationship can be used to convert that value into specific values for the one or more instance parameters. These values are then provided to the second transistor model for use in simulating the characteristics of the particular transistor during circuit simulation.
摘要:
Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.
摘要:
Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.
摘要:
Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.
摘要:
Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.
摘要:
An automated method for compensating for process-induced variations in threshold voltage and drive current in a MOSFET integrated circuit. The method's first step is selecting a transistor for analysis from the array. The method loops among the transistors of the array as desired. Next the design of the selected transistor is analyzed, including the steps of determining threshold voltage variations induced by layout neighborhood; determining drive current variations induced by layout neighborhood. The method then proceeds by attempting to compensate for any determined variations by varying the length of the transistor gate. The method can further include the step of identifying any shortcoming in compensation by varying contact spacing.
摘要:
Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel diffusions are not suppressed; preferably they have an elevation that is at least as high as that of the diffusion regions.
摘要:
Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel diffusions are not suppressed; preferably they have an elevation that is at least as high as that of the diffusion regions.
摘要:
An automated method for compensating for process-induced variations in threshold voltage and drive current in a MOSFET integrated circuit. The method's first step is selecting a transistor for analysis from the array. The method loops among the transistors of the array as desired. Next the design of the selected transistor is analyzed, including the steps of determining threshold voltage variations induced by layout neighborhood; determining drive current variations induced by layout neighborhood. The method then proceeds by attempting to compensate for any determined variations by varying the length of the transistor gate. The method can further include the step of identifying any shortcoming in compensation by varying contact spacing.