公开(公告)号：US07060573B2

公开(公告)日：2006-06-13

申请号：US09759909

申请日：2001-01-16

申请人： Victor Seng Keong Lim ,  Feng Chen ,  Lap Chan ,  Wang Ling Goh

发明人： Victor Seng Keong Lim ,  Feng Chen ,  Lap Chan ,  Wang Ling Goh

IPC分类号： H01L21/336

CPC分类号： H01L21/76232

摘要： A new method of forming shallow trench isolations has been described. A silicon semiconductor substrate is provided. A silicon nitride layer is deposited overlying the substrate. A polysilicon layer is deposited overlying the silicon nitride layer. An oxidation mask is deposited overlying the polysilicon layer. The oxidation mask, polysilicon layer, silicon nitride layer, and the silicon semiconductor substrate are patterned to form trenches for planned shallow trench isolations. The silicon semiconductor substrate exposed within the trenches is oxidized to form an oxide liner layer within the trenches wherein the oxidation mask prevents oxidation of the polysilicon layer. Thereafter the oxidation mask is removed. A trench oxide layer is deposited overlying the liner oxide layer and filling the trenches. The trench oxide layer and the polysilicon layer are polished down stopping at the silicon nitride layer with a polishing selectivity of oxide to polysilicon to nitride of 4:100:1 wherein dishing is avoided to complete shallow trench isolations in the manufacture of an integrated circuit device.

公开(公告)号：US06376376B1

公开(公告)日：2002-04-23

申请号：US09760165

申请日：2001-01-16

申请人： Victor Seng Keong Lim ,  Feng Chen ,  Wang Ling Goh

发明人： Victor Seng Keong Lim ,  Feng Chen ,  Wang Ling Goh

IPC分类号： H01L2144

CPC分类号： H01L21/7684

摘要： A new method of copper damascene metallization utilizing an additional oxide layer between the nitride and the barrier layers to prevent dishing of the copper line after CMP is described. An insulating layer is provided covering semiconductor device structures in and on a semiconductor substrate. A polish stop layer is deposited overlying the insulating layer. An oxide layer is deposited overlying the polish stop layer. An opening is etched through the oxide layer, the polish stop layer, and the insulating layer to one of the semiconductor device structures. A barrier metal layer is deposited over the surface of the oxide layer and within the opening. A copper layer is deposited over the surface of the barrier metal layer. The copper layer and the barrier metal layer not within the opening are polished away wherein the barrier metal layer polishes more slowly than the copper layer whereby dishing of the copper layer occurs. Thereafter, the oxide layer is polished away stopping at the polish stop layer wherein the oxide layer polishes more quickly than the copper layer whereby the dishing of the copper layer is removed and whereby a hump is formed on the copper layer after the oxide layer is completely polished away. The copper layer is overpolished to remove the hump to complete copper damascene metallization in the fabrication of an integrated circuit.

摘要翻译： 描述了利用在氮化物和阻挡层之间的附加氧化物层的铜镶嵌金属化的新方法，以防止CMP之后的铜线的凹陷。 提供了覆盖半导体衬底中的半导体器件结构的绝缘层。 覆盖在绝缘层上的抛光阻挡层被沉积。 沉积在抛光停止层上的氧化物层。 通过氧化物层，抛光停止层和绝缘层将开口蚀刻到半导体器件结构之一。 在氧化物层的表面和开口内沉积阻挡金属层。 在阻挡金属层的表面上沉积铜层。 铜层和不在开口内的阻挡金属层被抛光，其中阻挡金属层比铜层抛光得更慢，从而发生铜层的凹陷。 此后，在抛光停止层处停止氧化物层，其中氧化物层比铜层更快地抛光，由此去除铜层的凹陷，并且在氧化物层完全在铜层上形成隆起 抛光 在制造集成电路时，铜层被过度抛光以去除凸起以完成铜镶嵌金属化。

公开(公告)号：US06613649B2

公开(公告)日：2003-09-02

申请号：US10002873

申请日：2001-12-05

申请人： Seng-Keong Victor Lim ,  Feng Chen ,  Alex See ,  Wang Ling Goh

发明人： Seng-Keong Victor Lim ,  Feng Chen ,  Alex See ,  Wang Ling Goh

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： A method of manufacturing a shallow trench isolation using a polishing step with reduced dishing. A pad layer, a polish stop layer, a buffer layer and a hard mask layer are formed over a substrate. The hard mask layer has a hard mask opening. We etch a trench opening in the buffer layer, the polish stop layer, the pad layer and form a trench in the substrate using the hard mask layer as an etch mask. We form an oxide trench liner layer along the sidewalls of the trench and an oxide buffer liner layer on the sidewalls of the buffer layer using a thermal oxidation. The hard mask layer prevents the oxidation of the top surface of the buffer layer during the oxidation of the oxide trench liner. This prevents the buffer layer from being consumed by the oxidation and leaves the buffer layer to act in the subsequent chemical-mechanical polish (CMP) step. Next, an insulating layer is formed at least partially filling the trench. The insulating layer is chemical-mechanical polished using the polish stop layer as a stop layer. The buffer layer acts to prevent field oxide dishing during the chemical-mechanical polish.

摘要翻译： 使用具有减少的凹陷的抛光步骤制造浅沟槽隔离的方法。 在衬底上形成焊盘层，抛光停止层，缓冲层和硬掩模层。 硬掩模层具有硬掩模开口。 我们使用硬掩模层作为蚀刻掩模，在缓冲层，抛光停止层，焊盘层中蚀刻沟槽开口，并在衬底中形成沟槽。 我们使用热氧化沿着沟槽的侧壁和缓冲层的侧壁上的氧化物缓冲衬垫层形成氧化物沟槽衬里层。 硬掩模层防止在氧化物沟槽衬垫的氧化期间缓冲层的顶表面的氧化。 这防止缓冲层被氧化消耗，并使缓冲层在随后的化学 - 机械抛光（CMP）步骤中起作用。 接下来，形成至少部分地填充沟槽的绝缘层。 绝缘层使用抛光停止层作为停止层进行化学机械抛光。 缓冲层用于防止化学机械抛光过程中的场氧化物凹陷。

公开(公告)号：US06613648B1

公开(公告)日：2003-09-02

申请号：US10197354

申请日：2002-07-15

申请人： Seng-Keong Victor Lim ,  Feng Chen ,  Kong Hean Lee ,  Wang Ling Goh

发明人： Seng-Keong Victor Lim ,  Feng Chen ,  Kong Hean Lee ,  Wang Ling Goh

IPC分类号： H01L21762

CPC分类号： H01L21/76224

摘要： A method and apparatus for shallow trench isolation. First, a layer of silicon nitride (SiN) is deposited over a semiconductor substrate. A layer of polysilicon is then deposited over the silicon nitride layer. A layer of tetraethylorthosilicate (TEOS) is deposited over the polysilicon layer. Mask and etch steps are performed to form an opening that extends through the TEOS layer and through the polysilicon layer. An etch step is then performed to etch the exposed side surfaces of the polysilicon layer. Thereby, the exposed side surfaces of the polysilicon layer are moved laterally. An etch step is then performed so as to form a trench that extends into the semiconductor substrate. Dielectric material is deposited such that the dielectric material fills the trench and fills the opening that extends through the polysilicon layer and the silicon nitride layer. The substrate is then polished using a chemical mechanical polishing process. The chemical mechanical polishing process removes the polysilicon layer and forms a plug of dielectric material that fills the trench. The plug of dielectric material has a top surface that is planar with respect to the top of the silicon nitride layer.

摘要翻译： 浅沟槽隔离的方法和装置。 首先，在半导体衬底上沉积氮化硅层（SiN）。 然后在氮化硅层上沉积一层多晶硅。 在多晶硅层上沉积一层原硅酸四乙酯（TEOS）。 执行掩模和蚀刻步骤以形成延伸穿过TEOS层并穿过多晶硅层的开口。 然后执行蚀刻步骤以蚀刻多晶硅层的暴露的侧表面。 由此，多晶硅层的露出侧表面横向移动。 然后执行蚀刻步骤以形成延伸到半导体衬底中的沟槽。 介电材料被沉积成使得介电材料填充沟槽并填充延伸穿过多晶硅层和氮化硅层的开口。 然后使用化学机械抛光工艺抛光衬底。 化学机械抛光工艺去除多晶硅层并形成填充沟槽的电介质材料塞。 电介质材料的插塞具有相对于氮化硅层的顶部是平面的顶表面。

公开(公告)号：US06204137B1

公开(公告)日：2001-03-20

申请号：US09556386

申请日：2000-04-24

申请人： Kok Hin Teo ,  Feng Chen ,  Alex See ,  Lap Chan

发明人： Kok Hin Teo ,  Feng Chen ,  Alex See ,  Lap Chan

IPC分类号： H01L21336

CPC分类号： H01L29/66545 ,  H01L21/76224

摘要： A new method of forming MOS transistors has been achieved. A pad oxide layer is grown. A silicon nitride layer is deposited. Trenches are etched for planned STI. A trench liner is grown inside of the trenches. A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to complete the STI. The same silicon nitride layer is patterned to form dummy gates. A gate liner layer is deposited. Ions are implanted to form lightly doped drain junctions. Sidewall spacers are formed adjacent to the dummy gate electrodes and the shallow trench isolations. Ions are implanted to form the drain and source junctions. An epitaxial silicon layer is grown overlying the source and drain junctions. A metal layer is deposited. The epitaxial silicon layer is converted into sulicide to form silicided source and drain contacts. An interlevel dielectric layer is deposited and polished down to the dummy gates. The dummy gates are etched away to form openings for the planned transistor gates. A gate oxide layer is deposited lining the transistor gate openings. A gate electrode layer is deposited to fill the transistor gate openings. The gate electrode layer is patterned to complete the transistor gates.

摘要翻译： 已经实现了形成MOS晶体管的新方法。 生长衬垫氧化物层。 沉积氮化硅层。 沟槽蚀刻为计划的STI。 在沟槽内生长沟槽衬垫。 沉积填充沟槽的沟槽氧化物层。 将沟槽氧化物层抛光以完成STI。 将相同的氮化硅层图案化以形成伪栅极。 沉积栅极衬垫层。 植入离子以形成轻掺杂的漏极结。 侧壁间隔件形成在与虚拟栅极电极和浅沟槽隔离件相邻处。 植入离子以形成漏极和源极结。 生长在源极和漏极结上方的外延硅层。 沉积金属层。 将外延硅层转化为硅化物以形成硅化源极和漏极触点。 将层间电介质层沉积并抛光到虚拟栅极。 蚀刻掉虚拟栅极以形成预定晶体管栅极的开口。 在晶体管栅极开口上沉积栅极氧化物层。 沉积栅极电极层以填充晶体管栅极开口。 图案化栅极电极层以完成晶体管栅极。

公开(公告)号：US6103569A

公开(公告)日：2000-08-15

申请号：US459730

申请日：1999-12-13

申请人： Kok Hin Teo ,  Feng Chen ,  Lap Chan

发明人： Kok Hin Teo ,  Feng Chen ,  Lap Chan

IPC分类号： H01L21/321 ,  H01L21/768 ,  H01L21/8242

CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L21/76895

摘要： A method for planarizing metal plugs for device interconnections. The process begins by providing a semiconductor structure with at least one device thereon. A dielectric layer is formed over the device and the semiconductor structure. A first barrier metal layer is formed on the dielectric layer, and a sacrificial oxide layer is formed on the first barrier metal layer. The sacrificial oxide layer, the first barrier metal layer, and the dielectric layer are patterned to form contact openings. A second barrier metal layer is formed over the semiconductor structure, and a metal contact layer is formed on the second barrier metal layer. The metal contact layer and the second barrier metal layer are planarized using a first chemical mechanical polishing process and the sacrificial oxide layer is removed. The metal contact layer and the first barrier metal layer are planarized using a second chemical mechanical polishing process.

摘要翻译： 用于平面化用于器件互连的金属插头的方法。 该过程开始于在其上提供至少一个装置的半导体结构。 在器件和半导体结构上形成介电层。 在介电层上形成第一阻挡金属层，在第一阻挡金属层上形成牺牲氧化物层。 牺牲氧化物层，第一阻挡金属层和电介质层被图案化以形成接触开口。 在半导体结构上形成第二阻挡金属层，在第二阻挡金属层上形成金属接触层。 使用第一化学机械抛光工艺对金属接触层和第二阻挡金属层进行平面化处理，并去除牺牲氧化物层。 使用第二化学机械抛光工艺将金属接触层和第一阻挡金属层平坦化。

公开(公告)号：US06274485B1

公开(公告)日：2001-08-14

申请号：US09425310

申请日：1999-10-25

申请人： Feng Chen ,  Rick Teo ,  Lap Chan

发明人： Feng Chen ,  Rick Teo ,  Lap Chan

IPC分类号： H01L2144

CPC分类号： H01L21/7684

摘要： A new method of metal plug metallization utilizing a sacrificial high polishing rate layer to prevent dishing and metal residues after CMP is described. An oxide layer is provided overlying semiconductor device structures in and on a semiconductor substrate. A sacrificial high polishing rate (HPR) layer is deposited overlying the oxide layer. An opening is etched through the HPR layer and the oxide layer to one of the semiconductor device structures. A barrier layer and a metal layer are deposited over the surface of the HPR layer and within the opening. The metal layer, barrier layer, and HPR layer overlying the oxide layer are polished away by CMP. The polishing rate of the HPR layer is higher than that of the metal layer with the result that after the HPR layer is completely removed, the metal layer remaining within the opening has a convex shape. The oxide layer is over-polished until endpoint detection is received. Since the metal polishing rate is higher than the oxide polishing rate, the convex shape is made substantially planar during the over-polishing to complete metal plug metallization in the fabrication of an integrated circuit.

摘要翻译： 描述了利用牺牲高抛光速率层以防止CMP之后的凹陷和金属残余物的金属插塞金属化的新方法。 半导体衬底上半导体器件结构上覆盖氧化物层。 牺牲高抛光速率（HPR）层沉积在氧化物层上。 通过HPR层和氧化物层将开口蚀刻到半导体器件结构之一。 阻挡层和金属层沉积在HPR层的表面上并且在开口内。 覆盖氧化物层的金属层，阻挡层和HPR层通过CMP抛光。 HPR层的抛光速率高于金属层的抛光速率，结果是在HPR层被完全去除之后，残留在开口内的金属层具有凸形状。 氧化层被过度抛光，直到接收端点检测。 由于金属抛光速率高于氧化物研磨速度，因此在制造集成电路时，在抛光过程中使凸形形状基本上平坦，以完成金属插塞金属化。

公开(公告)号：USD998609S1

公开(公告)日：2023-09-12

申请号：US29887604

申请日：2023-03-22

申请人： Feng Chen

设计人： Feng Chen

摘要： FIG. 1 is a front, top perspective view of a switch portable dock showing my new design.
FIG. 2 is a front view thereof;
FIG. 3 is a rear view thereof;
FIG. 4 is a left side view thereof;
FIG. 5 is a right side view thereof;
FIG. 6 is a top view thereof;
FIG. 7 is a bottom view thereof;
FIG. 8 is a rear, bottom perspective view; and,
FIG. 9 is a front perspective view thereof, showing the switch portable dock in an open state of use.
The broken lines in the drawings depict portions of the switch portable dock that form no part of the claimed design.

公开(公告)号：US11265438B2

公开(公告)日：2022-03-01

申请号：US16978593

申请日：2018-04-26

申请人： Hewlett-Packard Development Company, L.P. ,  Da Peng Li ,  Zhi Wen Xing ,  Feng Chen

发明人： Da Peng Li ,  Zhi Wen Xing ,  Feng Chen

IPC分类号： H04N1/00 ,  H04N1/10 ,  G06F3/12

摘要： An example device includes a U-shaped body to be placed around a guide on which a scanner carriage is to be guided. A fixed leg of the U-shaped body is attached to a linearly translatable scanner carriage. A free leg of the U-shaped body is not attached to the scanner carriage and has inward facing ribs. The ribs on the free leg of the U-shaped body are positioned to come into contact with the guide to align the scanner carriage with the guide.

公开(公告)号：US10819535B2

公开(公告)日：2020-10-27

申请号：US16217556

申请日：2018-12-12

申请人： Feng Chen ,  Franz-Josef Götz ,  Marcel Kießling ,  An Ninh Nguyen ,  Jürgen Schmitt

发明人： Feng Chen ,  Franz-Josef Götz ,  Marcel Kießling ,  An Ninh Nguyen ,  Jürgen Schmitt

IPC分类号： G06F15/173 ,  H04L12/40 ,  H04L12/46 ,  H04L12/721 ,  H04L12/891 ,  H04L12/841 ,  H04L12/801 ,  H04L12/931

摘要： Methods and systems are provided for improved data packet transmission in a network bridge. Separate data packets received from a plurality of automation components are aggregated into a single data packet stream. The data packet stream is transmitted to another network node, for example, another network bridge.