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公开(公告)号：US07060573B2
公开(公告)日：2006-06-13
申请号：US09759909
申请日：2001-01-16
申请人： Victor Seng Keong Lim , Feng Chen , Lap Chan , Wang Ling Goh
发明人： Victor Seng Keong Lim , Feng Chen , Lap Chan , Wang Ling Goh
IPC分类号： H01L21/336
CPC分类号： H01L21/76232
摘要： A new method of forming shallow trench isolations has been described. A silicon semiconductor substrate is provided. A silicon nitride layer is deposited overlying the substrate. A polysilicon layer is deposited overlying the silicon nitride layer. An oxidation mask is deposited overlying the polysilicon layer. The oxidation mask, polysilicon layer, silicon nitride layer, and the silicon semiconductor substrate are patterned to form trenches for planned shallow trench isolations. The silicon semiconductor substrate exposed within the trenches is oxidized to form an oxide liner layer within the trenches wherein the oxidation mask prevents oxidation of the polysilicon layer. Thereafter the oxidation mask is removed. A trench oxide layer is deposited overlying the liner oxide layer and filling the trenches. The trench oxide layer and the polysilicon layer are polished down stopping at the silicon nitride layer with a polishing selectivity of oxide to polysilicon to nitride of 4:100:1 wherein dishing is avoided to complete shallow trench isolations in the manufacture of an integrated circuit device.
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公开(公告)号：US06403484B1
公开(公告)日：2002-06-11
申请号：US09803187
申请日：2001-03-12
申请人： Victor Seng Keong Lim , Lap Chan , James Lee , Chen Feng , Wang Ling Goh
发明人： Victor Seng Keong Lim , Lap Chan , James Lee , Chen Feng , Wang Ling Goh
IPC分类号： H01L2100
CPC分类号： H01L21/31056 , H01L21/31053 , H01L21/76229
摘要： A method of forming shallow trench isolations is described. A plurality of isolation trenches are etched through a first etch stop layer into the underlying semiconductor substrate. An oxide layer is deposited over the first etch stop layer and within the isolation trenches using a high density plasma chemical vapor deposition process (HDP-CVD) wherein after the oxide layer fills the isolation trenches, the deposition component is discontinued while continuing the sputtering component until corners of the first etch stop layer are exposed at edges of the isolation trenches whereby the oxide layer within the isolation trenches is disconnected from the oxide layer overlying the first etch stop layer. Thereafter, a second etch stop layer is deposited overlying the oxide layer within the isolation trenches, the oxide layer overlying the first etch stop layer, and the exposed first etch stop layer corners. The second etch stop layer is polished away until the oxide layer overlying the first etch stop layer is exposed. The exposed oxide layer overlying the first etch stop layer is removed. The first and second etch stop layers are removed to complete the planarized shallow trench isolation regions in the manufacture of an integrated circuit device.
摘要翻译： 描述了形成浅沟槽隔离的方法。 通过第一蚀刻停止层将多个隔离沟槽蚀刻到下面的半导体衬底中。 使用高密度等离子体化学气相沉积工艺（HDP-CVD）在第一蚀刻停止层和隔离沟槽内沉积氧化物层，其中在氧化物层填充隔离沟槽之后，沉积组分被中断，同时继续溅射组分 直到第一蚀刻停止层的角部暴露在隔离沟槽的边缘处，由此隔离沟槽内的氧化物层与覆盖在第一蚀刻停止层上的氧化物层断开。 此后，沉积在隔离沟槽内的氧化物层上的第二蚀刻停止层，覆盖在第一蚀刻停止层上的氧化物层和暴露的第一蚀刻停止层拐角。 将第二蚀刻停止层抛光，直到暴露出覆盖在第一蚀刻停止层上的氧化物层。 去除覆盖在第一蚀刻停止层上的暴露的氧化物层。 去除第一和第二蚀刻停止层以在集成电路器件的制造中完成平坦化的浅沟槽隔离区。
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公开(公告)号：US06376376B1
公开(公告)日：2002-04-23
申请号：US09760165
申请日：2001-01-16
申请人： Victor Seng Keong Lim , Feng Chen , Wang Ling Goh
发明人： Victor Seng Keong Lim , Feng Chen , Wang Ling Goh
IPC分类号： H01L2144
CPC分类号： H01L21/7684
摘要： A new method of copper damascene metallization utilizing an additional oxide layer between the nitride and the barrier layers to prevent dishing of the copper line after CMP is described. An insulating layer is provided covering semiconductor device structures in and on a semiconductor substrate. A polish stop layer is deposited overlying the insulating layer. An oxide layer is deposited overlying the polish stop layer. An opening is etched through the oxide layer, the polish stop layer, and the insulating layer to one of the semiconductor device structures. A barrier metal layer is deposited over the surface of the oxide layer and within the opening. A copper layer is deposited over the surface of the barrier metal layer. The copper layer and the barrier metal layer not within the opening are polished away wherein the barrier metal layer polishes more slowly than the copper layer whereby dishing of the copper layer occurs. Thereafter, the oxide layer is polished away stopping at the polish stop layer wherein the oxide layer polishes more quickly than the copper layer whereby the dishing of the copper layer is removed and whereby a hump is formed on the copper layer after the oxide layer is completely polished away. The copper layer is overpolished to remove the hump to complete copper damascene metallization in the fabrication of an integrated circuit.
摘要翻译： 描述了利用在氮化物和阻挡层之间的附加氧化物层的铜镶嵌金属化的新方法，以防止CMP之后的铜线的凹陷。 提供了覆盖半导体衬底中的半导体器件结构的绝缘层。 覆盖在绝缘层上的抛光阻挡层被沉积。 沉积在抛光停止层上的氧化物层。 通过氧化物层，抛光停止层和绝缘层将开口蚀刻到半导体器件结构之一。 在氧化物层的表面和开口内沉积阻挡金属层。 在阻挡金属层的表面上沉积铜层。 铜层和不在开口内的阻挡金属层被抛光，其中阻挡金属层比铜层抛光得更慢，从而发生铜层的凹陷。 此后，在抛光停止层处停止氧化物层，其中氧化物层比铜层更快地抛光，由此去除铜层的凹陷，并且在氧化物层完全在铜层上形成隆起 抛光 在制造集成电路时，铜层被过度抛光以去除凸起以完成铜镶嵌金属化。
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4.发明授权公开(公告)号：US06472697B2
公开(公告)日：2002-10-29
申请号：US10140574
申请日：2002-05-08
IPC分类号： H01L2710
CPC分类号： H01L21/76838 , H01L23/53219 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing conductive lines that are thicker (not wider) in the critical paths areas. We form a plurality of first level conductive lines over a first dielectric layer. The first conductive lines run in a first direction. The first level conductive lines are comprised of a first level first conductive line and a second first level conductive line. We form a second dielectric layer over the first level conductive lines and the first dielectric layer. Next, we form a via opening in the second dielectric layer over a portion of the first level first conductive line. A plug is formed filling the via opening. We form a trench pattern in the second dielectric layer. The trench pattern is comprised of trenches that are approximately orthogonal to the first level conductive lines. We fill the trenches with a conductive material to form supplemental second lines. We form second level conductive lines over the supplemental second lines and the plug. The second level conductive lines are aligned parallel to the supplemental second lines. The supplemental second lines are formed under the critical path areas of the second level conductive lines. The second level conductive lines are not formed to contact the first level conductive lines where a contact is not desired. In the critical path areas of the second level conductive lines, the supplemental second lines underlie the second level conductive lines thereby increasing the effective overall wiring thickness in the critical path area thereby improving performance.
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5.发明授权公开(公告)号：US06399471B1
公开(公告)日：2002-06-04
申请号：US09783379
申请日：2001-02-15
IPC分类号： H01L2144
CPC分类号： H01L21/76838 , H01L23/53219 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing conductive lines that are thicker (not wider) in the critical paths areas. We form a plurality of first level conductive lines over a first dielectric layer. The first conductive lines run in a first direction. The first level conductive lines are comprised of a first level first conductive line and a second first level conductive line. We form a second dielectric layer over the first level conductive lines and the first dielectric layer. Next, we form a via opening in the second dielectric layer over a portion of the first level first conductive line. A plug is formed filling the via opening. We form a trench pattern in the second dielectric layer. The trench pattern is comprised of trenches that are approximately orthogonal to the first level conductive lines. We fill the trenches with a conductive material to form supplemental second lines. We form second level conductive lines over the supplemental second lines and the plug. The second level conductive lines are aligned parallel to the supplemental second lines. The supplemental second lines are formed under the critical path areas of the second level conductive lines. The second level conductive lines are not formed to contact the first level conductive lines where a contact is not desired. In the critical path areas of the second level conductive lines, the supplemental second lines underlie the second level conductive lines thereby increasing the effective overall wiring thickness in the critical path area thereby improving performance.
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公开(公告)号：US08289508B2
公开(公告)日：2012-10-16
申请号：US12621510
申请日：2009-11-19
IPC分类号： G01N21/00
CPC分类号： H01L22/12
摘要： A method of forming a device is disclosed. The method includes providing a substrate and processing a layer of the device on the substrate. The layer is inspected with an inspection tool for defects. The inspection tool is programmed with an inspection recipe determined from studying defects programmed into the layer at known locations.
摘要翻译： 公开了一种形成装置的方法。 该方法包括提供衬底并在衬底上处理器件的一层。 该层用检查工具检查缺陷。 检查工具用从在已知位置处编程到层中的缺陷来确定的检查配方来编程。
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公开(公告)号：US08339449B2
公开(公告)日：2012-12-25
申请号：US12537269
申请日：2009-08-07
申请人： Barbara Fong Chin Lim , Keng Heng Lai , Tanya Yang , Victor Seng Keong Lim , Fang Hong Gn , Liang Choo Hsia
发明人： Barbara Fong Chin Lim , Keng Heng Lai , Tanya Yang , Victor Seng Keong Lim , Fang Hong Gn , Liang Choo Hsia
IPC分类号： H04N7/18
CPC分类号： G06T7/0006 , G01N21/9501 , G06T2207/10061 , G06T2207/30148
摘要： A method of forming a device is presented. The method includes providing a substrate containing at least a partially formed device thereon. The device comprises at least one defect site. A pixilated image of the defect site is acquired, and each pixel comprises a grey level value (GLV). Surrounding noises of the defect site is eliminated. A point of the image is identified as the center of the defect. A plurality of iterations to exclude outer edge pixels surrounding the center of the defect image is performed. The defect is categorized as a killer or non-killer defect.
摘要翻译： 提出了一种形成装置的方法。 该方法包括提供在其上至少包含部分形成的器件的衬底。 该装置包括至少一个缺陷部位。 获取缺陷部位的像素化图像，并且每个像素包括灰度值（GLV）。 消除了缺陷部位的周围噪声。 图像的一个点被识别为缺陷的中心。 执行多个迭代以排除围绕缺陷图像的中心的外边缘像素。 该缺陷被归类为杀伤或非杀伤性缺陷。
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公开(公告)号：US06815823B2
公开(公告)日：2004-11-09
申请号：US10679736
申请日：2003-10-06
IPC分类号： H01L2348
CPC分类号： H01L23/5226 , H01L21/31116 , H01L21/31138 , H01L21/76804 , H01L23/5283 , H01L23/53228 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A new method and structure is provided for the creation of interconnect lines. The cross section of the interconnect lines of the invention, taken in a plane that is perpendicular to the longitudinal direction of the interconnect lines, is a triangle as opposed to the conventional square or rectangular cross section of interconnect lines.
摘要翻译： 提供了一种新的方法和结构来创建互连线。 在与互连线的纵向方向垂直的平面中截取的本发明的互连线的横截面是与传统的互连线的矩形或矩形横截面相反的三角形。
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公开(公告)号：US07939348B2
公开(公告)日：2011-05-10
申请号：US11845787
申请日：2007-08-28
申请人： Victor Seng Keong Lim , Jeffrey Lam
发明人： Victor Seng Keong Lim , Jeffrey Lam
IPC分类号： H01L21/66
CPC分类号： H01L22/34 , G01R31/2884 , G01R31/307
摘要： A testing structure, and method of using the testing structure, where the testing structure comprised of at least one of eight test structures that exhibits a discernable defect characteristic upon voltage contrast scanning when it has at least one predetermined structural defect. The eight test structures being: 1) having an Active Area (AA)/P-N junction leakage; 2) having an isolation region to ground; 3) having an AA/P-N junction and isolation region; 4) having a gate dielectric leakage and gate to isolation region to ground; 5) having a gate dielectric leakage through AA/P-N junction to ground leakage; 6) having a gate dielectric to ground and gate/one side isolation region leakage to ground; 7) having an oversized gate dielectric through AA/P-N junction to ground leakage; and 8) having an AA/P-N junction leakage gate dielectric leakage.
摘要翻译： 测试结构和使用测试结构的方法，其中测试结构由八个测试结构中的至少一个组成，当电压对比度扫描具有至少一个预定的结构缺陷时，其具有可辨别的缺陷特征。 八个测试结构为：1）具有有源面积（AA）/ P-N结泄漏; 2）具有对地的隔离区域; 3）具有AA / P-N结和隔离区; 4）具有栅极电介质泄漏和栅极到隔离区域对地; 5）具有通过AA / P-N结到漏电的栅极电介质泄漏; 6）具有栅极电介质接地和栅极/一侧隔离区域泄漏到地面; 7）具有通过AA / P-N结到接地漏电的超大栅极电介质; 和8）具有AA / P-N结泄漏栅介质泄漏。
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公开(公告)号：US06649517B2
公开(公告)日：2003-11-18
申请号：US09859353
申请日：2001-05-18
IPC分类号： H01L214763
CPC分类号： H01L23/5226 , H01L21/31116 , H01L21/31138 , H01L21/76804 , H01L23/5283 , H01L23/53228 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A new method and structure is provided for the creation of interconnect lines. The cross section of the interconnect lines of the invention, taken in a plane that is perpendicular to the longitudinal direction of the interconnect lines, is a triangle as opposed to the conventional square or rectangular cross section of interconnect lines.
摘要翻译： 提供了一种新的方法和结构来创建互连线。 在与互连线的纵向方向垂直的平面中截取的本发明的互连线的横截面是与传统的互连线的矩形或矩形横截面相反的三角形。
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