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    AT-SPEED SCAN ENABLE SWITCHING CIRCUIT
    1.
    发明申请
    AT-SPEED SCAN ENABLE SWITCHING CIRCUIT 审中-公开
    AT速度扫描启用电路

    公开(公告)号：US20120176144A1

    公开(公告)日：2012-07-12

    申请号：US12986546

    申请日：2011-01-07

    申请人： Vikram Iyengar ,  Animesh Khare ,  Michael R. Ouellette ,  Narendra K. Rane ,  Umesh K. Shukla ,  Pradeep K. Vanama

    发明人： Vikram Iyengar ,  Animesh Khare ,  Michael R. Ouellette ,  Narendra K. Rane ,  Umesh K. Shukla ,  Pradeep K. Vanama

    IPC分类号： G01R27/28 ,  H01L25/00

    CPC分类号： G01R31/318572 ,  G01R31/318541

    摘要： A circuit for providing a local scan enable signal includes a first transistor having a first gate coupled to a general scan enable signal, a first source and a first drain and a second transistor having a second gate coupled to a scan clock, a second source coupled to the first drain and a second drain. The circuit also includes a third transistor having a third gate coupled to the general scan enable signal, a third drain coupled to the second drain and a third source and an output stabilizer coupled to the second drain, the output stabilizer including a first inverter and a second inverter coupled together in opposite orientations.

    摘要翻译： 用于提供本地扫描使能信号的电路包括具有耦合到一般扫描使能信号的第一栅极的第一晶体管，第一源极和第一漏极以及耦合到扫描时钟的第二栅极的第二晶体管， 到第一排水口和第二排水管。 电路还包括第三晶体管，其具有耦合到通用扫描使能信号的第三栅极，耦合到第二漏极的第三漏极和耦合到第二漏极的第三源极和输出稳定器，输出稳定器包括第一反相器和 第二个逆变器以相反的方向耦合在一起。

    Reducing power consumption during manufacturing test of an integrated circuit
    4.
    发明授权
    Reducing power consumption during manufacturing test of an integrated circuit 有权
    降低集成电路制造试验期间的功耗

    公开(公告)号：US09043180B2

    公开(公告)日：2015-05-26

    申请号：US13369642

    申请日：2012-02-09

    申请人： Vikram Iyengar ,  Animesh Khare ,  Kenneth Pichamuthu

    发明人： Vikram Iyengar ,  Animesh Khare ,  Kenneth Pichamuthu

    IPC分类号： G01N33/48 ,  G01R31/3185

    CPC分类号： G01R31/318314 ,  G01R31/318307 ,  G01R31/318575

    摘要： Aspects of the invention provide for reducing power consumption during manufacturing testing of an IC. In one embodiment, aspects of the invention include a method for reducing power consumption during a manufacturing test of an integrated circuit (IC), the method including: providing a plurality of domains, each domain associated with a clock phase; grouping, based on each domain, a first plurality of scan chains into a first test group; grouping, based on each domain, a second plurality of scan chains into a second test group, wherein the grouping of the first test group and of the second test group includes determining which domains can be tested simultaneously; and performing the manufacturing test of the IC.

    摘要翻译： 本发明的方面提供了在IC的制造测试期间降低功耗。 在一个实施例中，本发明的方面包括一种用于在集成电路（IC）的制造测试期间降低功耗的方法，所述方法包括：提供多个域，每个域与时钟相关联; 将基于每个域的第一多个扫描链分组成第一测试组; 基于每个域将第二多个扫描链分组成第二测试组，其中第一测试组和第二测试组的分组包括确定可以同时测试哪些结构域; 并进行IC的制造测试。

    REDUCING POWER CONSUMPTION DURING MANUFACTURING TEST OF AN INTEGRATED CIRCUIT
    5.
    发明申请
    REDUCING POWER CONSUMPTION DURING MANUFACTURING TEST OF AN INTEGRATED CIRCUIT 有权
    在集成电路的制造测试期间降低功耗

    公开(公告)号：US20130211769A1

    公开(公告)日：2013-08-15

    申请号：US13369642

    申请日：2012-02-09

    申请人： Vikram Iyengar ,  Animesh Khare ,  Kenneth Pichamuthu

    发明人： Vikram Iyengar ,  Animesh Khare ,  Kenneth Pichamuthu

    IPC分类号： G06F19/00

    CPC分类号： G01R31/318314 ,  G01R31/318307 ,  G01R31/318575

    摘要： Aspects of the invention provide for reducing power consumption during manufacturing testing of an IC. In one embodiment, aspects of the invention include a method for reducing power consumption during a manufacturing test of an integrated circuit (IC), the method including: providing a plurality of domains, each domain associated with a clock phase; grouping, based on each domain, a first plurality of scan chains into a first test group; grouping, based on each domain, a second plurality of scan chains into a second test group, wherein the grouping of the first test group and of the second test group includes determining which domains can be tested simultaneously; and performing the manufacturing test of the IC.

    摘要翻译： 本发明的方面提供了在IC的制造测试期间降低功耗。 在一个实施例中，本发明的方面包括一种用于在集成电路（IC）的制造测试期间降低功耗的方法，所述方法包括：提供多个域，每个域与时钟相关联; 将基于每个域的第一多个扫描链分组成第一测试组; 基于每个域将第二多个扫描链分组成第二测试组，其中第一测试组和第二测试组的分组包括确定可以同时测试哪些结构域; 并进行IC的制造测试。

    Automated isolation of logic and macro blocks in chip design testing
    6.
    发明授权
    Automated isolation of logic and macro blocks in chip design testing 有权
    在芯片设计测试中自动隔离逻辑和宏块

    公开(公告)号：US08132133B2

    公开(公告)日：2012-03-06

    申请号：US12196840

    申请日：2008-08-22

    申请人： Animesh Khare ,  Narendra Keshav Rane

    发明人： Animesh Khare ,  Narendra Keshav Rane

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022 ,  G06F2217/14

    摘要： A method and system for testing a synthesized design of a semiconductor chip. The method includes inputting a macro test Input/Output (I/O) name of the semiconductor chip, along with associated attributes and a netlist, where the netlist is a synthesized design of the semiconductor chip. The method includes tracking the macro test I/O to a chip test I/O. The method further includes detecting mismatches between attributes associated with the macro test I/O and the chip test I/O. Subsequently, reporting any mismatches between the attributes associated with the macro test I/O and the chip test I/O.

    摘要翻译： 一种用于测试半导体芯片的合成设计的方法和系统。 该方法包括输入半导体芯片的宏测试输入/输出（I / O）名称以及相关属性和网表，其中网表是半导体芯片的合成设计。 该方法包括将宏测试I / O跟踪到芯片测试I / O。 该方法还包括检测与宏测试I / O相关联的属性与芯片测试I / O之间的不匹配。 随后，报告与宏测试I / O相关联的属性与芯片测试I / O之间的任何不匹配。

    AUTOMATED ISOLATION OF LOGIC AND MACRO BLOCKS IN CHIP DESIGN TESTING
    7.
    发明申请
    AUTOMATED ISOLATION OF LOGIC AND MACRO BLOCKS IN CHIP DESIGN TESTING 有权
    自动分离芯片设计测试中的逻辑和宏块

    公开(公告)号：US20100050137A1

    公开(公告)日：2010-02-25

    申请号：US12196840

    申请日：2008-08-22

    申请人： Animesh Khare ,  Narendra Keshav Rane

    发明人： Animesh Khare ,  Narendra Keshav Rane

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022 ,  G06F2217/14

    摘要： A method and system for testing a synthesized design of a semiconductor chip. The method includes inputting a macro test Input/Output (I/O) name of the semiconductor chip, along with associated attributes and a netlist, where the netlist is a synthesized design of the semiconductor chip. The method includes tracking the macro test I/O to a chip test I/O. The method further includes detecting mismatches between attributes associated with the macro test I/O and the chip test I/O. Subsequently, reporting any mismatches between the attributes associated with the macro test I/O and the chip test I/O.

    摘要翻译： 一种用于测试半导体芯片的合成设计的方法和系统。 该方法包括输入半导体芯片的宏测试输入/输出（I / O）名称以及相关属性和网表，其中网表是半导体芯片的合成设计。 该方法包括将宏测试I / O跟踪到芯片测试I / O。 该方法还包括检测与宏测试I / O相关联的属性与芯片测试I / O之间的不匹配。 随后，报告与宏测试I / O相关联的属性与芯片测试I / O之间的任何不匹配。