利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

33 条记录 (耗时 0.033 秒)

    Reduced overhead address mode change management in a pipelined, recycling microprocessor
    1.
    发明授权
    Reduced overhead address mode change management in a pipelined, recycling microprocessor 失效
    在流水线回收微处理器中减少开销地址模式更改管理

    公开(公告)号：US07971034B2

    公开(公告)日：2011-06-28

    申请号：US12051415

    申请日：2008-03-19

    申请人： David S. Hutton ,  Michael Billeci ,  Fadi Y. Busaba ,  Brian R. Prasky ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum ,  Charles F. Webb

    发明人： David S. Hutton ,  Michael Billeci ,  Fadi Y. Busaba ,  Brian R. Prasky ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum ,  Charles F. Webb

    IPC分类号： G06F9/00 ,  G06F9/44 ,  G06F9/30

    CPC分类号： G06F9/30189 ,  G06F9/30076 ,  G06F9/342 ,  G06F9/3802 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3861 ,  G06F9/3867

    摘要： A method, system, and computer program product for reduced overhead address mode change management in a pipelined, recycling microprocessor are provided. The recycling microprocessor includes logic executing thereon. The microprocessor also includes an instruction fetch unit (IFU) supporting computation of address adds in selected address modes and reporting non-equal comparison of the computation to the logic. The microprocessor further includes a fixed point unit determining whether the mode has changed and reporting changes to the logic. Upon determining the comparison yields an equal result but the mode has changed, a recycle event is triggered to ensure subsequent ofetches are relaunched in the correct mode and that no execution writebacks occur from work performed in an incorrect mode. For comparisons yielding a non-equal result and a changed mode, the logic clears bits set in response to the determinations, and a serialization event is taken to reset a corresponding pipeline for operation in the correct mode.

    摘要翻译： 提供了一种用于在流水线式回收微处理器中减少开销地址模式改变管理的方法，系统和计算机程序产品。 回收微处理器包括在其上执行的逻辑。 微处理器还包括一个指令提取单元（IFU），用于支持在所选择的地址模式中添加的地址的计算，并且将该计算的不相等的比较报告给逻辑。 微处理器还包括确定模式是否改变并且对逻辑进行报告改变的固定点单元。 在确定比较时，产生相等的结果，但是模式已经改变，触发一个循环事件，以确保以正确的模式重新启动后续的提取，并且在不正确的模式下执行的工作不会执行执行回写。 为了比较产生不相等的结果和改变的模式，逻辑清除响应于确定的位设置，并且采用串行化事件来复位相应的流水线以便以正确的模式进行操作。

    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR REDUCED OVERHEAD ADDRESS MODE CHANGE MANAGEMENT IN A PIPELINED, RECYLING MICROPROCESSOR
    2.
    发明申请
    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR REDUCED OVERHEAD ADDRESS MODE CHANGE MANAGEMENT IN A PIPELINED, RECYLING MICROPROCESSOR 失效
    方法，系统和计算机程序产品，用于在管道，回收微处理器中减少地址模式更改管理

    公开(公告)号：US20090240929A1

    公开(公告)日：2009-09-24

    申请号：US12051415

    申请日：2008-03-19

    申请人： David S. Hutton ,  Michael Billeci ,  Fadi Y. Busaba ,  Brian R. Prasky ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum ,  Charles F. Webb

    发明人： David S. Hutton ,  Michael Billeci ,  Fadi Y. Busaba ,  Brian R. Prasky ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum ,  Charles F. Webb

    IPC分类号： G06F9/312

    CPC分类号： G06F9/30189 ,  G06F9/30076 ,  G06F9/342 ,  G06F9/3802 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3861 ,  G06F9/3867

    摘要： A method, system, and computer program product for reduced overhead address mode change management in a pipelined, recycling microprocessor are provided. The recycling microprocessor includes logic executing thereon. The microprocessor also includes an instruction fetch unit (IFU) supporting computation of address adds in selected address modes and reporting non-equal comparison of the computation to the logic. The microprocessor further includes a fixed point unit determining whether the mode has changed and reporting changes to the logic. Upon determining the comparison yields an equal result but the mode has changed, a recycle event is triggered to ensure subsequent ofetches are relaunched in the correct mode and that no execution writebacks occur from work performed in an incorrect mode. For comparisons yielding a non-equal result and a changed mode, the logic clears bits set in response to the determinations, and a serialization event is taken to reset a corresponding pipeline for operation in the correct mode.

    摘要翻译： 提供了一种用于在流水线式回收微处理器中减少开销地址模式改变管理的方法，系统和计算机程序产品。 回收微处理器包括在其上执行的逻辑。 微处理器还包括一个指令提取单元（IFU），用于支持在所选择的地址模式中添加的地址的计算，并且将该计算的不相等的比较报告给逻辑。 微处理器还包括确定模式是否改变并且对逻辑进行报告改变的固定点单元。 在确定比较时，产生相等的结果，但是模式已经改变，触发一个循环事件，以确保以正确的模式重新启动后续的提取，并且在不正确的模式下执行的工作不会执行执行回写。 为了比较产生不相等的结果和改变的模式，逻辑清除响应于确定的位设置，并且采用串行化事件来复位相应的流水线以便以正确的模式进行操作。

    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR SUPPORTING PARTIAL RECYCLE IN A PIPELINED MICROPROCESSOR
    3.
    发明申请
    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR SUPPORTING PARTIAL RECYCLE IN A PIPELINED MICROPROCESSOR 有权
    用于支持管道微处理器部分回收的方法，系统和计算机程序产品

    公开(公告)号：US20090240921A1

    公开(公告)日：2009-09-24

    申请号：US12051486

    申请日：2008-03-19

    申请人： Khary J. Alexander ,  Michael Billeci ,  Fadi Y. Busaba ,  Bruce C. Giamei

    发明人： Khary J. Alexander ,  Michael Billeci ,  Fadi Y. Busaba ,  Bruce C. Giamei

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3865 ,  G06F9/3836 ,  G06F9/3842

    摘要： A computer processing system is provided. The computer processing system includes a first datastore that stores a subset of information associated with an instruction. A first stage of a processor pipeline writes the subset of information to the first datastore based on an execution of an operation associated with the instruction. A second stage of the pipeline initiates reprocessing of the operation associated with the instruction based on the subset of information stored in the first datastore.

    摘要翻译： 提供了一种计算机处理系统。 计算机处理系统包括存储与指令相关联的信息的子集的第一数据存储区。 处理器流水线的第一阶段基于与指令相关联的操作的执行将信息子集写入第一数据存储区。 管道的第二阶段基于存储在第一数据存储区中的信息子集来启动与指令相关联的操作的再处理。

    Supporting partial recycle in a pipelined microprocessor
    5.
    发明授权
    Supporting partial recycle in a pipelined microprocessor 有权
    支持流水线微处理器的部分回收

    公开(公告)号：US08516228B2

    公开(公告)日：2013-08-20

    申请号：US12051486

    申请日：2008-03-19

    申请人： Khary J. Alexander ,  Michael Billeci ,  Fadi Y. Busaba ,  Bruce C. Giamei

    发明人： Khary J. Alexander ,  Michael Billeci ,  Fadi Y. Busaba ,  Bruce C. Giamei

    IPC分类号： G06F9/00

    CPC分类号： G06F9/3865 ,  G06F9/3836 ,  G06F9/3842

    摘要： A computer processing system is provided. The computer processing system includes a first datastore that stores a subset of information associated with an instruction. A first stage of a processor pipeline writes the subset of information to the first datastore based on an execution of an operation associated with the instruction. A second stage of the pipeline initiates reprocessing of the operation associated with the instruction based on the subset of information stored in the first datastore.

    摘要翻译： 提供了一种计算机处理系统。 计算机处理系统包括存储与指令相关联的信息的子集的第一数据存储区。 处理器流水线的第一阶段基于与指令相关联的操作的执行将信息子集写入第一数据存储区。 管道的第二阶段基于存储在第一数据存储区中的信息子集来启动与指令相关联的操作的再处理。

    Processor error checking for instruction data
    6.
    发明授权
    Processor error checking for instruction data 有权
    处理器错误检查指令数据

    公开(公告)号：US08201067B2

    公开(公告)日：2012-06-12

    申请号：US12037038

    申请日：2008-02-25

    申请人： Fadi Y. Busaba ,  Khary J. Alexander ,  Michael Billeci ,  Bruce C. Giamei ,  Vimal M. Kapadia

    发明人： Fadi Y. Busaba ,  Khary J. Alexander ,  Michael Billeci ,  Bruce C. Giamei ,  Vimal M. Kapadia

    IPC分类号： G06F11/00 ,  G08C25/00 ,  H03M13/00 ,  H04L1/00

    CPC分类号： G06F11/10

    摘要： A method for processor error checking including receiving an instruction data, generating a pre-processing parity data based on the instruction data, maintaining the pre-processing parity data, processing the instruction data, generating a post-processing parity data based on the processed instruction data, checking for an error related to processing the instruction data by comparing the post-processing parity data to the pre-processing parity data, and transmitting an error signal that indicates the error related to processing the instruction data occurred if the post-processing parity data does not match the pre-processing parity data, wherein checking for the error related to processing the instruction data is performed without using a duplicate processing circuitry.

    摘要翻译： 一种用于处理器错误检查的方法，包括接收指令数据，基于指令数据产生预处理奇偶校验数据，维持预处理奇偶校验数据，处理指令数据，基于处理指令产生后处理奇偶校验数据 数据，通过将后处理奇偶校验数据与预处理奇偶校验数据进行比较来检查与处理指令数据相关的错误，以及如果后处理奇偶校验数据发送指示与处理指令数据相关的错误的错误信号 数据与预处理奇偶校验数据不匹配，其中在不使用重复处理电路的情况下执行检查与处理指令数据有关的错误。

    METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR PROCESSOR ERROR CHECKING
    7.
    发明申请
    METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR PROCESSOR ERROR CHECKING 有权
    用于处理器错误检查的方法，系统和计算机程序产品

    公开(公告)号：US20090217077A1

    公开(公告)日：2009-08-27

    申请号：US12037038

    申请日：2008-02-25

    申请人： Fadi Y. Busaba ,  Khary J. Alexander ,  Michael Billeci ,  Bruce C. Giamei ,  Vimal M. Kapadia

    发明人： Fadi Y. Busaba ,  Khary J. Alexander ,  Michael Billeci ,  Bruce C. Giamei ,  Vimal M. Kapadia

    IPC分类号： G06F11/07

    CPC分类号： G06F11/10

    摘要： A method for processor error checking including receiving an instruction data, generating a pre-processing parity data based on the instruction data, maintaining the pre-processing parity data, processing the instruction data, generating a post-processing parity data based on the processed instruction data, checking for an error related to processing the instruction data by comparing the post-processing parity data to the pre-processing parity data, and transmitting an error signal that indicates the error related to processing the instruction data occurred if the post-processing parity data does not match the pre-processing parity data, wherein checking for the error related to processing the instruction data is performed without using a duplicate processing circuitry.

    摘要翻译： 一种用于处理器错误检查的方法，包括接收指令数据，基于指令数据产生预处理奇偶校验数据，维持预处理奇偶校验数据，处理指令数据，基于处理指令产生后处理奇偶校验数据 数据，通过将后处理奇偶校验数据与预处理奇偶校验数据进行比较来检查与处理指令数据相关的错误，以及如果后处理奇偶校验数据发送指示与处理指令数据相关的错误的错误信号 数据与预处理奇偶校验数据不匹配，其中在不使用重复处理电路的情况下执行检查与处理指令数据有关的错误。

    Method and apparatus for mirroring units within a processor
    9.
    发明授权
    Method and apparatus for mirroring units within a processor 失效
    用于在处理器内镜像单元的方法和装置

    公开(公告)号：US07082550B2

    公开(公告)日：2006-07-25

    申请号：US10435914

    申请日：2003-05-12

    申请人： Michael Billeci ,  Chung-Lung K. Shum ,  Timothy J. Slegel

    发明人： Michael Billeci ,  Chung-Lung K. Shum ,  Timothy J. Slegel

    IPC分类号： G06F11/16

    CPC分类号： G06F11/1695 ,  G06F11/1641

    摘要： A processor responsive to a clock cycle includes a base-unit, a mirror-unit that is a duplicate instance of the base-unit, a non-duplicate-unit in signal communication with the base and mirror units, a first staging register disposed at the input to the mirror-unit for delaying the input signal thereto by at least one clock cycle, and a second staging register disposed at the output of the mirror-unit for delaying the output signal therefrom by at least one clock cycle. The non-duplicate-unit includes a comparator for comparing the output signals of the base and mirror units.

    摘要翻译： 响应于时钟周期的处理器包括基本单元，作为基本单元的重复实例的镜像单元，与基础单元和镜像单元进行信号通信的非重复单元，第一分段寄存器，其布置在 用于将输入信号延迟至少一个时钟周期的反射镜单元的输入，以及设置在镜单元的输出处的第二分段寄存器，用于将其输出信号延迟至少一个时钟周期。 非重复单元包括用于比较基座和反射镜单元的输出信号的比较器。

    Method and system for performing a hardware trace
    10.
    发明申请
    Method and system for performing a hardware trace 有权
    执行硬件跟踪的方法和系统

    公开(公告)号：US20050022068A1

    公开(公告)日：2005-01-27

    申请号：US10616635

    申请日：2003-07-10

    申请人： Michael Billeci ,  Timothy Slegel

    发明人： Michael Billeci ,  Timothy Slegel

    IPC分类号： G06F11/00 ,  G06F11/22

    CPC分类号： G06F11/2268

    摘要： An embodiment of the invention is a method for capturing hardware trace data. A wrap-back address space is defined and during compression mode, trace data is circularly stored in the wrap-back address space. Upon exiting compression mode, a write address is established for further trace data such that trace data prior to existing compression mode is maintained.

    摘要翻译： 本发明的实施例是用于捕获硬件跟踪数据的方法。 定义回绕地址空间，在压缩模式期间，跟踪数据循环存储在回绕地址空间中。 在退出压缩模式时，为进一步的跟踪数据建立写入地址，使得维持现有压缩模式之前的跟踪数据。