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公开(公告)号：US08097498B2
公开(公告)日：2012-01-17
申请号：US12693322
申请日：2010-01-25
IPC分类号： H01L21/20
CPC分类号： H01L27/101 , H01L27/1021
摘要： A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device level, patterning the sacrificial layer and the first semiconductor rails in the first device level to form a plurality of second rails extending in a second direction, wherein the plurality of second rails extend at least partially into the first device level and are separated from each other by rail shaped openings which extend at least partially into the first device level, forming second insulating features between the plurality of second rails, removing the sacrificial layer, and forming second semiconductor rails between the second insulating features in a second device level over the first device level. The first semiconductor rails extend in a first direction. The second semiconductor rails extend in the second direction different from the first direction.
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2.发明授权Lithographically space-defined charge storage regions in non-volatile memory 有权非易失性存储器中的光刻空间定义电荷存储区域公开(公告)号：US07807529B2
公开(公告)日：2010-10-05
申请号：US11960513
申请日：2007-12-19
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： Lithographically-defined spacing is used to define feature sizes during fabrication of semiconductor-based memory devices. Sacrificial features are formed over a substrate at a specified pitch having a line size and a space size defined by a photolithography pattern. Charge storage regions for storage elements are formed in the spaces between adjacent sacrificial features using the lithographically-defined spacing to fix a gate length or dimension of the charge storage regions in a column direction. Unequal line and space sizes at the specified pitch can be used to form feature sizes at less than the minimally resolvable feature size associated with the photolithography process. Larger line sizes can improve line-edge roughness while decreasing the dimension of the charge storage regions in the column direction. Additional charge storage regions for the storage elements can be formed over the charge storage regions so defined, such as by depositing and etching a second charge storage layer to form second charge storage regions having a dimension in the column direction that is less than the gate length of the first charge storage regions.
摘要翻译： 在制造基于半导体的存储器件期间，使用光刻定义的间距来定义特征尺寸。 牺牲特征以具有由光刻图案限定的线尺寸和空间尺寸的指定间距在衬底上形成。 用于存储元件的电荷存储区域使用光刻定义的间隔在相邻的牺牲特征之间的空间中形成，以将电荷存储区域的栅极长度或尺寸固定在列方向上。 可以使用指定间距处的不等的线和空间尺寸来形成小于与光刻工艺相关联的最小可解析特征尺寸的特征尺寸。 较大的线尺寸可以改善线边缘粗糙度，同时减小电荷存储区域在列方向上的尺寸。 存储元件的附加电荷存储区域可以形成在如此限定的电荷存储区域上，例如通过沉积和蚀刻第二电荷存储层以形成具有小于栅极长度的列方向尺寸的第二电荷存储区域 的第一电荷存储区域。
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3.发明申请Composite Charge Storage Structure Formation In Non-Volatile Memory Using Etch Stop Technologies 有权使用蚀刻停止技术在非易失性存储器中的复合电荷存储结构形成公开(公告)号：US20100055889A1
公开(公告)日：2010-03-04
申请号：US12615154
申请日：2009-11-09
IPC分类号： H01L21/28
CPC分类号： H01L27/11521 , H01L29/42324 , H01L29/7881
摘要： Semiconductor-based non-volatile memory that includes memory cells with composite charge storage elements is fabricated using an etch stop layer during formation of at least a portion of the storage element. One composite charge storage element suitable for memory applications includes a first charge storage region having a larger gate length or dimension in a column direction than a second charge storage region. While not required, the different regions can be formed of the same or similar materials, such as polysilicon. Etching a second charge storage layer selectively with respect to a first charge storage layer can be performed using an interleaving etch-stop layer. The first charge storage layer is protected from overetching or damage during etching of the second charge storage layer. Consistency in the dimensions of the individual memory cells can be increased.
摘要翻译： 包括具有复合电荷存储元件的存储器单元的基于半导体的非易失性存储器在形成存储元件的至少一部分期间使用蚀刻停止层制造。 适用于存储器应用的一个复合电荷存储元件包括具有比第二电荷存储区域在列方向上更大的栅极长度或尺寸的第一电荷存储区域。 虽然不需要，但是不同的区域可以由相同或相似的材料形成，例如多晶硅。 可以使用交错蚀刻停止层来执行相对于第一电荷存储层选择性地蚀刻第二电荷存储层。 第一电荷存储层在第二电荷存储层的蚀刻期间被保护以免过蚀或损坏。 可以增加各个存储单元尺寸的一致性。
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4.发明授权公开(公告)号：US08546152B2
公开(公告)日：2013-10-01
申请号：US11960485
申请日：2007-12-19
IPC分类号： H01L21/66
CPC分类号： H01L22/26 , H01L27/11521
摘要： A method of fabricating non-volatile memory is provided for memory cells employing a charge storage element with multiple charge storage regions. A first charge storage layer is formed over a tunnel dielectric layer at both a memory array region and an endpoint region of a semiconductor substrate. The first charge storage layer is removed from the endpoint region to expose the tunnel dielectric region. A second charge storage layer is formed over the first charge storage layer at the memory array region and over the tunnel dielectric layer at the endpoint region. When etching the second charge storage layer to form the stem regions of the memory cells, the tunnel dielectric layer provides a detectable endpoint signal to indicate that etching for the second charge storage layer is complete.
摘要翻译： 提供一种制造非易失性存储器的方法，用于采用具有多个电荷存储区域的电荷存储元件的存储单元。 第一电荷存储层在半导体衬底的存储器阵列区域和端点区域的隧道电介质层上形成。 从端点区域去除第一电荷存储层以暴露隧道电介质区域。 第二电荷存储层形成在存储器阵列区域的第一电荷存储层上，并在端点区域的隧道电介质层上形成。 当蚀刻第二电荷存储层以形成存储器单元的干区域时，隧道介电层提供可检测的端点信号，以指示第二电荷存储层的蚀刻完成。
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5.发明授权Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer 有权使用耦合层的包括自对准金属纳米点的浮栅形成存储器的方法公开(公告)号：US08263465B2
公开(公告)日：2012-09-11
申请号：US12754408
申请日：2010-04-05
IPC分类号： H01L21/339
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42332 , Y10S438/962 , Y10S977/72 , Y10S977/81 , Y10S977/943
摘要： Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.
摘要翻译： 提供了用于制造具有金属纳米点作为电荷存储元件的存储器的技术。 在示例性方法中，在基板上的栅极氧化物层上提供诸如氨基官能的硅烷基团之类的耦合层。 将基底浸渍在具有金属纳米点的胶体溶液中，使得纳米点附着到偶联层中的位置。 然后通过漂洗或氮吹干燥将溶剂层溶解，将纳米点留在栅极氧化物层上。 纳米点与偶联层反应并变成负电荷并排列成均匀的单层，排斥另外的单层纳米点的沉积。 在使用包括纳米点的高k电介质浮动栅极上的控制栅极的配置中，可以通过蚀刻来分离控制栅极，同时浮栅绝缘体不间断延伸，因为纳米点彼此电隔离。
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6.发明授权Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer 有权使用耦合层的包括自对准金属纳米点的浮栅形成存储器的方法公开(公告)号：US07723186B2
公开(公告)日：2010-05-25
申请号：US11958941
申请日：2007-12-18
IPC分类号： H01L21/336 , H01L21/30
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42332 , Y10S438/962 , Y10S977/72 , Y10S977/81 , Y10S977/943
摘要： Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.
摘要翻译： 提供了用于制造具有金属纳米点作为电荷存储元件的存储器的技术。 在示例性方法中，在基板上的栅极氧化物层上提供诸如氨基官能的硅烷基团之类的耦合层。 将基底浸渍在具有金属纳米点的胶体溶液中，使得纳米点附着到偶联层中的位置。 然后通过漂洗或氮吹干燥将溶剂层溶解，将纳米点留在栅极氧化物层上。 纳米点与偶联层反应并变成负电荷并排列成均匀的单层，排斥另外的单层纳米点的沉积。 在使用包括纳米点的高k电介质浮动栅极上的控制栅极的配置中，可以通过蚀刻来分离控制栅极，同时浮栅绝缘体不间断延伸，因为纳米点彼此电隔离。
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7.发明授权Composite charge storage structure formation in non-volatile memory using etch stop technologies 有权使用蚀刻停止技术在非易失性存储器中形成复合电荷存储结构公开(公告)号：US07939407B2
公开(公告)日：2011-05-10
申请号：US12615154
申请日：2009-11-09
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L29/42324 , H01L29/7881
摘要： Semiconductor-based non-volatile memory that includes memory cells with composite charge storage elements is fabricated using an etch stop layer during formation of at least a portion of the storage element. One composite charge storage element suitable for memory applications includes a first charge storage region having a larger gate length or dimension in a column direction than a second charge storage region. While not required, the different regions can be formed of the same or similar materials, such as polysilicon. Etching a second charge storage layer selectively with respect to a first charge storage layer can be performed using an interleaving etch-stop layer. The first charge storage layer is protected from overetching or damage during etching of the second charge storage layer. Consistency in the dimensions of the individual memory cells can be increased.
摘要翻译： 包括具有复合电荷存储元件的存储器单元的基于半导体的非易失性存储器在形成存储元件的至少一部分期间使用蚀刻停止层制造。 适用于存储器应用的一个复合电荷存储元件包括具有比第二电荷存储区域在列方向上更大的栅极长度或尺寸的第一电荷存储区域。 虽然不需要，但是不同的区域可以由相同或相似的材料形成，例如多晶硅。 可以使用交错蚀刻停止层来执行相对于第一电荷存储层选择性地蚀刻第二电荷存储层。 第一电荷存储层在第二电荷存储层的蚀刻期间被保护以免过蚀或损坏。 可以增加各个存储单元尺寸的一致性。
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8.发明申请Lithographically Space-Defined Charge Storage Regions In Non-Volatile Memory 有权非易失性存储器中的光刻空间定义电荷存储区域公开(公告)号：US20090163008A1
公开(公告)日：2009-06-25
申请号：US11960513
申请日：2007-12-19
IPC分类号： H01L21/28
CPC分类号： H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： Lithographically-defined spacing is used to define feature sizes during fabrication of semiconductor-based memory devices. Sacrificial features are formed over a substrate at a specified pitch having a line size and a space size defined by a photolithography pattern. Charge storage regions for storage elements are formed in the spaces between adjacent sacrificial features using the lithographically-defined spacing to fix a gate length or dimension of the charge storage regions in a column direction. Unequal line and space sizes at the specified pitch can be used to form feature sizes at less than the minimally resolvable feature size associated with the photolithography process. Larger line sizes can improve line-edge roughness while decreasing the dimension of the charge storage regions in the column direction. Additional charge storage regions for the storage elements can be formed over the charge storage regions so defined, such as by depositing and etching a second charge storage layer to form second charge storage regions having a dimension in the column direction that is less than the gate length of the first charge storage regions.
摘要翻译： 在制造基于半导体的存储器件期间，使用光刻定义的间距来定义特征尺寸。 牺牲特征以具有由光刻图案限定的线尺寸和空间尺寸的指定间距在衬底上形成。 用于存储元件的电荷存储区域使用光刻定义的间隔在相邻的牺牲特征之间的空间中形成，以将电荷存储区域的栅极长度或尺寸固定在列方向上。 可以使用指定间距处的不等的线和空间尺寸来形成小于与光刻工艺相关联的最小可解析特征尺寸的特征尺寸。 较大的线尺寸可以改善线边缘粗糙度，同时减小电荷存储区域在列方向上的尺寸。 存储元件的附加电荷存储区域可以形成在如此限定的电荷存储区域上，例如通过沉积和蚀刻第二电荷存储层以形成具有小于栅极长度的列方向尺寸的第二电荷存储区域 的第一电荷存储区域。
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9.发明申请公开(公告)号：US20090162951A1
公开(公告)日：2009-06-25
申请号：US11960485
申请日：2007-12-19
IPC分类号： H01L21/66
CPC分类号： H01L22/26 , H01L27/11521
摘要： A method of fabricating non-volatile memory is provided for memory cells employing a charge storage element with multiple charge storage regions. A first charge storage layer is formed over a tunnel dielectric layer at both a memory array region and an endpoint region of a semiconductor substrate. The first charge storage layer is removed from the endpoint region to expose the tunnel dielectric region. A second charge storage layer is formed over the first charge storage layer at the memory array region and over the tunnel dielectric layer at the endpoint region. When etching the second charge storage layer to form the stem regions of the memory cells, the tunnel dielectric layer provides a detectable endpoint signal to indicate that etching for the second charge storage layer is complete.
摘要翻译： 提供一种制造非易失性存储器的方法，用于采用具有多个电荷存储区域的电荷存储元件的存储单元。 第一电荷存储层在半导体衬底的存储器阵列区域和端点区域的隧道电介质层上形成。 从端点区域去除第一电荷存储层以暴露隧道电介质区域。 第二电荷存储层形成在存储器阵列区域的第一电荷存储层上，并在端点区域的隧道电介质层上形成。 当蚀刻第二电荷存储层以形成存储器单元的干区域时，隧道介电层提供可检测的端点信号，以指示第二电荷存储层的蚀刻完成。
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10.发明授权Method of forming memory with floating gates including self-aligned metal nanodots using a polymer solution 有权使用聚合物溶液形成包括自对准金属纳米点的浮栅的存储器的方法公开(公告)号：US08193055B1
公开(公告)日：2012-06-05
申请号：US11958875
申请日：2007-12-18
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , B82Y40/00 , H01L27/11521 , H01L29/42332 , Y10S977/72 , Y10S977/81
摘要： Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, metal salt ions are added to a core of a copolymer solution. A metal salt reduction causes the metal atoms to aggregate in the core, forming a metal nanodot. The copolymer solution is applied to a gate oxide on a substrate using spin coating or dip coating. Due to the copolymer configuration, the nanodots are held in a uniform 2D grid on the gate oxide. The polymers are selected to provide a desired nanodot size and spacing between nanodots. A polymer cure and removal process leaves the nanodots on the gate oxide. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.
摘要翻译： 提供了用于制造具有金属纳米点作为电荷存储元件的存储器的技术。 在一个示例性方法中，将金属盐离子加入到共聚物溶液的芯中。 金属盐还原导致金属原子在芯中聚集，形成金属纳米点。 使用旋涂或浸涂将共聚物溶液施加到基板上的栅极氧化物上。 由于共聚物构型，纳米点被保持在栅极氧化物上的均匀的2D栅格中。 选择聚合物以在纳米点之间提供期望的纳米尺寸和间隔。 聚合物固化和去除过程使栅极氧化物上的纳米点离开。 在使用包括纳米点的高k电介质浮动栅极上的控制栅极的配置中，可以通过蚀刻来分离控制栅极，同时浮栅绝缘体不间断延伸，因为纳米点彼此电隔离。
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