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    Circuit for linearizing electronic devices
    1.
    发明授权
    Circuit for linearizing electronic devices 有权
    线性化电子设备的电路

    公开(公告)号：US06717463B2

    公开(公告)日：2004-04-06

    申请号：US09961460

    申请日：2001-09-21

    申请人： Vladimir Aparin ,  Peter J. Shah

    发明人： Vladimir Aparin ,  Peter J. Shah

    IPC分类号： H03F126

    CPC分类号： H03F1/32 ,  H03F1/34 ,  H03F3/19

    摘要： A radio frequency amplifier with improved linearity and minimal third-order distortion. The amplifier includes a first transistor having first, second and third terminals with the first terminal being an input terminal and the second terminal being the output terminal and the third terminal being a common terminal. A linearization circuit is included having first and second terminals. The first terminal is connected to the common terminal of the transistor and the second terminal is connected to the input terminal of the transistor. In a specific embodiment, the linearization circuit is implemented as a unity gain buffer with an input terminal connected to the common terminal of the transistor and an output terminal connected to the input terminal of the transistor. In accordance with the inventive teachings, the buffer has a low gain and high output impedance at first frequency (f1) of a first signal applied to the circuit and a second frequency (f2) of a second signal applied to the circuit and a unity gain and low output impedance a difference between the first and second frequencies. In another specific embodiment, the inductor is inserted between the output of the unity gain buffer and the input terminal of the transistor. In alternative embodiments, circuitry is shown for providing a direct current offset at the input of the transistor. As another alternative, the linearization circuit consists of series inductor and capacitor connected between the common and input terminals of the transistor. In yet another embodiment, the linearization circuit consists of the first and the second series inductor and capacitor circuits. The first series LC circuit is connected between the common terminal of the transistor and ground and the second series LC circuit is connected between the input terminal of the transistor and ground.

    摘要翻译： 具有改善线性度和最小三阶失真的射频放大器。 放大器包括具有第一，第二和第三端子的第一晶体管，第一端子是输入端子，第二端子是输出端子，第三端子是公共端子。 包括具有第一和第二端子的线性化电路。 第一端子连接到晶体管的公共端子，第二端子连接到晶体管的输入端子。 在具体实施例中，线性化电路被实现为具有连接到晶体管的公共端子的输入端子和连接到晶体管的输入端子的输出端子的单位增益缓冲器。 根据本发明，缓冲器在施加到电路的第一信号的第一频率（f1）处施加低增益和高输出阻抗，以及施加到电路的第二信号的第二频率（f2）和单位增益 并且低输出阻抗是第一和第二频率之间的差。 在另一个具体实施例中，电感器插入在单位增益缓冲器的输出端和晶体管的输入端子之间。 在替代实施例中，示出了用于在晶体管的输入处提供直流偏移的电路。 作为另一种选择，线性化电路由连接在晶体管的公共端和输入端之间的串联电感和电容组成。 在另一个实施例中，线性化电路由第一和第二串联电感器和电容器电路组成。 第一串联LC电路连接在晶体管的公共端和地之间，第二串联LC电路连接在晶体管的输入端和地之间。

    METHOD AND APPARATUS FOR UNSUPERVISED TRAINING OF INPUT SYNAPSES OF PRIMARY VISUAL CORTEX SIMPLE CELLS AND OTHER NEURAL CIRCUITS
    4.
    发明申请
    METHOD AND APPARATUS FOR UNSUPERVISED TRAINING OF INPUT SYNAPSES OF PRIMARY VISUAL CORTEX SIMPLE CELLS AND OTHER NEURAL CIRCUITS 有权
    主要视觉CORTEX简单细胞和其他神经电路输入信号的不间断训练的方法和装置

    公开(公告)号：US20120303566A1

    公开(公告)日：2012-11-29

    申请号：US13115154

    申请日：2011-05-25

    申请人： Vladimir Aparin

    发明人： Vladimir Aparin

    IPC分类号： G06N3/08 ,  G06N3/063

    CPC分类号： G06N3/063

    摘要： Certain aspects of the present disclosure present a technique for unsupervised training of input synapses of primary visual cortex (V1) simple cells and other neural circuits. The proposed unsupervised training method utilizes simple neuron models for both Retinal Ganglion Cell (RGC) and V1 layers. The model simply adds the weighted inputs of each cell, wherein the inputs can have positive or negative values. The resulting weighted sums of inputs represent activations that can also be positive or negative. In an aspect of the present disclosure, the weights of each V1 cell can be adjusted depending on a sign of corresponding RGC output and a sign of activation of that V1 cell in the direction of increasing the absolute value of the activation. The RGC-to-V1 weights can be positive and negative for modeling ON and OFF RGCs, respectively.

    摘要翻译： 本公开的某些方面提供了用于无监督训练初级视皮层（V1）简单细胞和其他神经电路的输入突触的技术。 提出的无监督训练方法使用简单的神经元模型用于视网膜神经节细胞（RGC）和V1层。 该模型简单地添加每个单元的加权输入，其中输入可以具有正值或负值。 所得的加权输入总和代表也可以是正或负的激活。 在本公开的一方面，可以根据对应的RGC输出的符号和在增加激活的绝对值的方向激活该V1小区的符号来调整每个V1小区的权重。 RGC-to-V1权重可以分别为ON和OFF RGC的正负值。

    HIGH-SPEED HIGH-POWER SEMICONDUCTOR DEVICES
    6.
    发明申请
    HIGH-SPEED HIGH-POWER SEMICONDUCTOR DEVICES 有权
    高速大功率半导体器件

    公开(公告)号：US20120211812A1

    公开(公告)日：2012-08-23

    申请号：US13103918

    申请日：2011-05-09

    申请人： Yang Du ,  Vladimir Aparin ,  Robert P. Gilmore

    发明人： Yang Du ,  Vladimir Aparin ,  Robert P. Gilmore

    IPC分类号： H01L29/94 ,  H01L21/8238

    CPC分类号： H01L29/0653 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/402 ,  H01L29/42384 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/78624 ,  H01L29/78645

    摘要： High-speed high-power semiconductor devices are disclosed. In an exemplary design, a high-speed high-power semiconductor device includes a source, a drain to provide an output signal, and an active gate to receive an input signal. The semiconductor device further includes at least one field gate located between the active gate and the drain, at least one shallow trench isolation (STI) strip formed transverse to the at least one field gate, and at least one drain active strip formed parallel to, and alternating with, the at least one STI strip. The semiconductor device may be modeled by a combination of an active FET and a MOS varactor. The active gate controls the active FET, and the at least one field gate controls the MOS varactor. The semiconductor device has a low on resistance and can handle a high voltage.

    摘要翻译： 公开了高速大功率半导体器件。 在示例性设计中，高速大功率半导体器件包括源极，提供输出信号的漏极和用于接收输入信号的有源栅极。 所述半导体器件还包括位于有源栅极和漏极之间的至少一个场栅极，至少一个横向于至少一个场栅极形成的浅沟槽隔离（STI）条和至少一个平行于该栅极的漏极有源条， 并与所述至少一个STI条交替。 半导体器件可以通过有源FET和MOS变容二极管的组合来建模。 有源栅极控制有源FET，并且至少一个场门控制MOS变容二极管。 半导体器件具有低导通电阻并且可以处理高电压。

    COMMUNICATION AND SYNAPSE TRAINING METHOD AND HARDWARE FOR BIOLOGICALLY INSPIRED NETWORKS
    8.
    发明申请
    COMMUNICATION AND SYNAPSE TRAINING METHOD AND HARDWARE FOR BIOLOGICALLY INSPIRED NETWORKS 有权
    通信和仿真培训方法和生物信息网络的硬件

    公开(公告)号：US20120011088A1

    公开(公告)日：2012-01-12

    申请号：US12831540

    申请日：2010-07-07

    申请人： Vladimir Aparin ,  Yi Tang

    发明人： Vladimir Aparin ,  Yi Tang

    IPC分类号： G06N3/063 ,  G06N3/08

    CPC分类号： G06N3/0635 ,  G06N3/02 ,  G06N3/06 ,  G06N3/08 ,  G06N99/005

    摘要： Certain embodiments of the present disclosure support techniques for training of synapses in biologically inspired networks. Only one device based on a memristor can be used as a synaptic connection between a pair of neurons. The training of synaptic weights can be achieved with a low current consumption. A proposed synapse training circuit may be shared by a plurality of incoming/outgoing connections, while only one digitally implemented pulse-width modulation (PWM) generator can be utilized per neuron circuit for generating synapse-training pulses. Only up to three phases of a slow clock can be used for both the neuron-to-neuron communications and synapse training. Some special control signals can be also generated for setting up synapse training events. By means of these signals, the synapse training circuit can be in a high-impedance state outside the training events, thus the synaptic resistance (i.e., the synaptic weight) is not affected outside the training process.

    摘要翻译： 本公开的某些实施例支持在生物启发网络中训练突触的技术。 只有一个基于忆阻器的设备可以用作一对神经元之间的突触连接。 突触体重的训练可以用低电流消耗来实现。 所提出的突触训练电路可以由多个输入/输出连接共享，而每个神经元电路只能使用一个数字实现的脉宽调制（PWM）发生器来产生突触训练脉冲。 只有三个阶段的慢时钟可以用于神经元到神经元通信和突触训练。 还可以生成一些特殊的控制信号来设置突触训练事件。 通过这些信号，突触训练电路可以在训练事件之外处于高阻抗状态，因此在训练过程之外不会影响突触电阻（即突触重量）。

    METHOD AND APPARATUS FOR USING PRE-DISTORTION AND FEEDBACK TO MITIGATE NONLINEARITY OF CIRCUITS
    9.
    发明申请
    METHOD AND APPARATUS FOR USING PRE-DISTORTION AND FEEDBACK TO MITIGATE NONLINEARITY OF CIRCUITS 审中-公开
    使用预失真和反馈来减轻电路非线性的方法和装置

    公开(公告)号：US20100323641A1

    公开(公告)日：2010-12-23

    申请号：US12489380

    申请日：2009-06-22

    申请人： Vladimir Aparin ,  Gary John Ballantyne

    发明人： Vladimir Aparin ,  Gary John Ballantyne

    IPC分类号： H04B1/04

    CPC分类号： H03F1/34 ,  H03F1/3258

    摘要： Techniques for mitigating nonlinearity of circuits with both pre-distortion and feedback are described. An apparatus may include at least one circuit (e.g., an upconverter, a power amplifier, etc.), a pre-distortion circuit, and a feedback circuit. The circuit(s) may generate an output signal having distortion components due to their nonlinearity. The pre-distortion circuit may receive an input signal and generate a pre-distorted signal based on at least one coefficient determined by the nonlinearity of the circuit(s). The pre-distortion circuit may adaptively determine the coefficient(s) based on the input signal and an error signal. The feedback circuit may generate the error signal based on the input signal and the output signal and may filter the error signal to obtain a filtered error signal. The circuit(s) may process the pre-distorted signal and the filtered error signal to generate the output signal, which may have attenuated distortion components due to pre-distortion and feedback.

    摘要翻译： 描述了减轻预失真和反馈的电路非线性的技术。 装置可以包括至少一个电路（例如，上变频器，功率放大器等），预失真电路和反馈电路。 电路可以由于它们的非线性而产生具有失真分量的输出信号。 预失真电路可以接收输入信号，并且基于由电路的非线性确定的至少一个系数产生预失真信号。 预失真电路可以基于输入信号和误差信号自适应地确定系数。 反馈电路可以基于输入信号和输出信号产生误差信号，并且可以对误差信号进行滤波以获得滤波后的误差信号。 电路可以处理预失真信号和滤波后的误差信号以产生输出信号，其可能由于预失真和反馈而具有衰减的失真分量。

    REDUCTION OF SECOND-ORDER DISTORTION CAUSED BY TRANSMIT SIGNAL LEAKAGE
    10.
    发明申请
    REDUCTION OF SECOND-ORDER DISTORTION CAUSED BY TRANSMIT SIGNAL LEAKAGE 有权
    减少由发射信号泄漏引起的二次失真

    公开(公告)号：US20080233894A1

    公开(公告)日：2008-09-25

    申请号：US11690173

    申请日：2007-03-23

    申请人： Vladimir Aparin

    发明人： Vladimir Aparin

    IPC分类号： H04B1/44

    CPC分类号： H04B1/525 ,  H04B1/30

    摘要： This disclosure describes techniques for reducing adverse effects of TX signal leakage in a full-duplex, wireless communication system. In particular, the disclosure describes techniques for reducing adverse effects of second order distortion of TX signal leakage. To reduce or eliminate second order distortion of transmit signal leakage, a wireless device squares a combined signal that carries both a desired RX signal and a TX leakage signal. For example, the device may include a device that exhibits a strong, second order nonlinearity to, in effect, square the combined signal. The device subtracts the squared signal from the output of the mixer in the receive path, canceling out at least some of the second-order distortion caused by the mixer. In this manner, the device can reduce the adverse effects of second order distortion of TX signal leakage, and thereby enhance or maintain receiver sensitivity.

    摘要翻译： 本公开描述了用于减少全双工无线通信系统中TX信号泄漏的不利影响的技术。 具体地，本公开描述了用于减少TX信号泄漏的二阶失真的不利影响的技术。 为了减少或消除发射信号泄漏的二阶失真，无线设备对携带期望的RX信号和TX泄漏信号的组合信号进行平方。 例如，该装置可以包括展现强的二阶非线性的装置，其实际上对于组合信号的平方。 该装置从接收路径中的混频器的输出中减去平方信号，消除由混频器引起的至少一些二阶失真。 以这种方式，该装置可以减少TX信号泄漏的二阶失真的不利影响，从而提高或维持接收机灵敏度。