公开(公告)号：US4638265A

公开(公告)日：1987-01-20

申请号：US740366

申请日：1985-06-03

申请人： Gerald K. Lunn ,  W. Eric Main ,  Michael McGinn

发明人： Gerald K. Lunn ,  W. Eric Main ,  Michael McGinn

IPC分类号： H03H11/46 ,  H03H11/48 ,  H03H7/48

CPC分类号： H03H11/483

摘要： A variable reactance, the value of which is controllable, is produced between a pair of terminals of a variable reactance circuit comprising a pair of current steering circuits. First and second reactive components are coupled respectively between the pair of terminals and the first and second current steering circuits to produce first and second antiphase reactive currents'. The first reactive current is split by the first current steering circuit into first and second antiphased proportional currents. Likewise, the second reactive current is split by the second current steering circuit into third and fourth antiphased proportional currents with said first and third currents being antiphased with respect to each other. The first reactive current is summed at a first one of the pair of terminals with said first and third currents while the second reactive current is summed at the second one of the pair of terminals with said second and fourth currents to produce the variable reactance across the terminals.

摘要翻译： 在包括一对电流转向电路的可变电抗电路的一对端子之间产生其值可控的可变电抗。 第一和第二无功分量分别耦合在该对端子与第一和第二电流转向电路之间以产生第一和第二反相电流。 第一无功电流由第一电流转向电路分为第一和第二反相比例电流。 类似地，第二无功电流由第二电流转向电路分裂成第三和第四反相比例电流，所述第一和第三电流相对于彼此反相。 第一无功电流在具有所述第一和第三电流的一对端子中的第一个处被相加，而第二无功电流在所述第二和第四电流的一对端子中的第二无功电流相加以产生跨越所述第一和第三电流的可变电抗 终端。

公开(公告)号：US4567388A

公开(公告)日：1986-01-28

申请号：US538241

申请日：1983-10-03

申请人： Robert B. Jarrett ,  W. Eric Main ,  Robert A. Neidorff

发明人： Robert B. Jarrett ,  W. Eric Main ,  Robert A. Neidorff

IPC分类号： H03K5/08 ,  H03K19/003

CPC分类号： H03K5/08 ,  H03K19/00307

摘要： This relates to a circuit for clamping the voltage across first and second terminals (in this case the gate and source electrodes of a power MOSFET) in response to the receipt of a signal indicating a load fault. An input turnaround transistor receives the signal indicative of the fault and generates a current in response thereto which is applied to the base of a switching transistor. When this current exceeds a predetermined value, the switching transistor turns on which in turn causes a buffer circuit including a PNP transistor to turn on. When the buffer circuit turns on, current is drawn through a zener diode which is coupled to the second terminal. Thus, the clamping circuit between the gate and source terminals equals the voltage drop across the zener diode plus that dropped across the buffer circuit plus the saturation voltage of the switching transistor. Resistors are provided in the buffer circuit to provide for a certain amount of adjustment of the clamping voltage.

摘要翻译： 这涉及用于响应于接收到指示负载故障的信号而夹紧跨越第一和第二端子（在这种情况下是功率MOSFET的栅极和源极）的电压的电路。 输入周转晶体管接收指示故障的信号，并响应于此产生施加到开关晶体管的基极的电流。 当该电流超过预定值时，开关晶体管导通，这又导致包括PNP晶体管的缓冲电路导通。 当缓冲电路导通时，电流通过耦合到第二端子的齐纳二极管引出。 因此，栅极和源极端子之间的钳位电路等于齐纳二极管上的压降加上缓冲电路上的压降加开关晶体管的饱和电压。 缓冲电路中提供电阻器，以提供钳位电压的一定量的调整。

公开(公告)号：US5497123A

公开(公告)日：1996-03-05

申请号：US363089

申请日：1994-12-23

申请人： W. Eric Main ,  Jeffrey C. Durec

发明人： W. Eric Main ,  Jeffrey C. Durec

IPC分类号： H03F3/45 ,  H03D7/14 ,  H03F1/32 ,  H03F1/42 ,  H03F3/343

CPC分类号： H03F1/3211 ,  H03D7/1433 ,  H03D7/1491 ,  H03D2200/0033 ,  H03D2200/0043

摘要： A amplifier (21) having increased linearity, low input impedance, and low noise is provided. The amplifier (21) has an input (22), a bias input, a first output (23), and a second output (33). A first transistor (26) has a collector coupled to the first output (23), a base coupled to the bias input, and an emitter. A first resistor (27) is coupled between the emitter of the first transistor (26) and the input (22). A second transistor (29) has a collector and base coupled in common, and an emitter coupled for receiving a power supply voltage. A second resistor (28) couples between the input (22) and the common base and collector of the second transistor (29). A third transistor (32) has a collector coupled to the second output (33), a base coupled to the common base and collector of the second transistor (29), and an emitter coupled for receiving the power supply voltage. An input signal applied to the input (22) generates a differential current at the first and second outputs (23, 33). The input signal and the differential current have a linear relationship.

摘要翻译： 提供了具有增加的线性度，低输入阻抗和低噪声的放大器（21）。 放大器（21）具有输入（22），偏置输入，第一输出（23）和第二输出（33）。 第一晶体管（26）具有耦合到第一输出（23）的集电极，耦合到偏置输入的基极和发射极。 第一电阻器（27）耦合在第一晶体管（26）的发射极和输入端（22）之间。 第二晶体管（29）具有共同耦合的集电极和基极，以及用于接收电源电压的发射极。 第二电阻器（28）耦合在输入端（22）和第二晶体管（29）的公共基极和集电极之间。 第三晶体管（32）具有耦合到第二输出（33）的集电极，耦合到第二晶体管（29）的公共基极和集电极的基极，以及耦合以接收电源电压的发射极。 施加到输入端（22）的输入信号在第一和第二输出（23,33）处产生差动电流。 输入信号和差分电流有线性关系。

公开(公告)号：US4385364A

公开(公告)日：1983-05-24

申请号：US203013

申请日：1980-11-03

申请人： W. Eric Main

发明人： W. Eric Main

IPC分类号： H03G1/00 ,  H03G7/00 ,  G06G7/12 ,  G06G7/16

CPC分类号： H03G7/002 ,  H03G1/0005

摘要： An electronic gain control circuit comprising a logarithmic circuit portion and an antilogarithmic circuit portion which is coupled to a current mirror circuit producing an output signal which is linearly related to an input signal applied to the logarithmic circuit portion thereof having a magnitude which is varied in response to a gain-control signal applied to the circuit. The logarithmic circuit portion of the gain control circuit provides a logarithmic voltage drive signal which drives the antilogarithmic circuit portion to supply an input current at the input of the current mirror having no fundamental signal components of the applied input signal. The output of the antilogarithmic circuit portion is coupled at an interconnect node with the output of the current mirror such that direct current components as well as second harmonic signal components of the applied input signal are cancelled and do not appear in the output of the electronic gain control circuit.

摘要翻译： 一种电子增益控制电路，包括对数电路部分和反对数电路部分，该对数电路部分耦合到电流镜电路，产生与施加到其对数电路部分的输入信号线性相关的输出信号，该输入信号的响应幅度变化 涉及施加到电路的增益控制信号。 增益控制电路的对数电路部分提供对数电压驱动信号，其驱动反对数电路部分，以在电流镜的输入端提供输入电流，该输入电流不具有所施加的输入信号的基本信号分量。 反对数电路部分的输出在互连节点处与电流镜的输出耦合，使得所施加的输入信号的直流分量以及二次谐波信号分量被消除并且不出现在电子增益的输出中 控制电路。

公开(公告)号：US4878031A

公开(公告)日：1989-10-31

申请号：US319038

申请日：1989-03-06

申请人： W. Eric Main

发明人： W. Eric Main

IPC分类号： H03G3/00

CPC分类号： H03G3/00

摘要： A variable gain control circuit comprising an input stage and an output stage is responsive to an applied input signal for providing an output signal. The input stage and output stage are independently biased by respective bias sources and each include circuitry responsive to a dynamic control voltage, the latter of which is generated in response to the input signal, to permit the absolute magnitudes of the input signal and output signal to exceed the respective bias sources. The ratio of the output and input signals is proportional to the ratio of the bias sources.

摘要翻译： 包括输入级和输出级的可变增益控制电路响应于所施加的输入信号以提供输出信号。 输入级和输出级由相应的偏置源独立地偏置，并且每个包括响应于动态控制电压的电路，后者是响应于输入信号产生的，以允许输入信号的绝对幅度和输出信号 超过相应的偏压源。 输出和输入信号的比例与偏置源的比例成比例。

公开(公告)号：US4633195A

公开(公告)日：1986-12-30

申请号：US800231

申请日：1985-11-21

申请人： W. Eric Main

发明人： W. Eric Main

IPC分类号： H03B5/12 ,  H03B5/08 ,  H03C3/00

CPC分类号： H03B5/1215 ,  H03B5/1231 ,  H03B2200/0062 ,  H03B2200/0098

摘要： A balanced LC oscillator for providing differential oscillator output signals includes a pair of transistors the emitters of which are connected to a voltage reference source that provides a fixed voltage thereto. The base electrodes of each transistor is cross coupled to the collector of the other transistor. The LC tank circuit is connected between the collectors of the two transistors and current supply is provided thereto. Although the potential at the bases of the two transistors vary with respect to the oscillator signal appearing thereat, the emitters are held at a fixed potential to eliminate any common mode signal that may otherwise be generated if the potential at the emitters was permitted to vary.

摘要翻译： 用于提供差分振荡器输出信号的平衡LC振荡器包括一对晶体管，其发射极连接到向其提供固定电压的电压参考源。 每个晶体管的基极电极交叉耦合到另一个晶体管的集电极。 LC槽电路连接在两个晶体管的集电极之间，并向其供电。 尽管在两个晶体管的基极上的电位相对于出现的振荡器信号而变化，但是发射极保持固定的电位，以消除任何共模信号，否则在发射极处的电位被允许变化的情况下可能产生。

公开(公告)号：US5457424A

公开(公告)日：1995-10-10

申请号：US318940

申请日：1994-10-06

申请人： Michael McGinn ,  W. Eric Main

发明人： Michael McGinn ,  W. Eric Main

IPC分类号： H04L27/152 ,  H04L27/38

CPC分类号： H04L27/1525

摘要： A demodulation circuit (10) performs quadrature demodulation on an IF input signal. The IF input signal processes through a preamplifier (12) to one input of a mixer (14). The mixer output goes to first and second multipliers (20, 22). A VCO (24) generates an oscillator signal that processes through a first multiplier (26) and first and second dividers (28, 30) to generate in-phase and quadrature recovered carrier signals that are applied to second inputs of the first and second multipliers which in turn produce the in-phase and quadrature demodulated baseband signals. A switching arrangement (32, 38, 40) for the multiplier and dividers provides the proper frequency signal to a second input of the mixer to generate sum and difference frequencies. A filter and amplifier at the output of the mixer removes the summation frequency leaving the difference frequency to the first and second multipliers.

摘要翻译： 解调电路（10）对IF输入信号进行正交解调。 IF输入信号通过前置放大器（12）处理到混频器（14）的一个输入端。 混频器输出转到第一和第二乘法器（20,22）。 VCO（24）产生振荡器信号，其通过第一乘法器（26）和第一和第二分频器（28,30）进行处理，以产生施加到第一和第二乘法器的第二输入端的同相和正交恢复的载波信号 这又产生同相和正交解调的基带信号。 用于乘法器和分频器的开关装置（32,38,40）向混频器的第二输入端提供适当的频率信号以产生和和差频率。 在混频器的输出处的滤波器和放大器将离差值的求和频率除去到第一和第二乘法器。

公开(公告)号：US4728815A

公开(公告)日：1988-03-01

申请号：US919349

申请日：1986-10-16

申请人： W. Eric Main

发明人： W. Eric Main

IPC分类号： H03K5/01 ,  H03K5/007 ,  H03K5/08 ,  H03K17/60 ,  H03K17/66 ,  H04L25/03 ,  H04L27/14 ,  H04L27/152 ,  H03K5/00 ,  G05F3/16 ,  H03F3/45

CPC分类号： H03K17/60 ,  H03K17/667 ,  H03K5/08

摘要： A circuit for producing output pulses in response to an alternating signal supplied to the input thereof which is comprised of a pair of complementary transistors cascoded between a pair of current mirror circuits which source and sink currents to and from a common terminal respectively. The alternating input signal is applied to the interconnected emitters of the two transistors thereby rendering one more conductive while the other is rendered less conductive and vice versa. The currents which are sourced or sunk at the common terminal are proportional to the currents flowing in the two transistors and are compared to cause an output transistor to switch operating states thereby producing the output pulse.

摘要翻译： 一种用于响应于提供给其输入的交流信号产生输出脉冲的电路，该电路由一对互补晶体管组成，该对互补晶体管分别串联在一对电流镜电路之间，该电流镜电路分别与公共端的源极和吸收电流之间。 交替的输入信号被施加到两个晶体管的互连的发射器，从而再一个导电，而另一个被导通更少导电，反之亦然。 在公共端子处产生或沉没的电流与在两个晶体管中流动的电流成比例，并且被比较以使输出晶体管切换操作状态，从而产生输出脉冲。

公开(公告)号：US4517547A

公开(公告)日：1985-05-14

申请号：US323643

申请日：1981-11-20

申请人： Randall C. Gray ,  W. Eric Main

发明人： Randall C. Gray ,  W. Eric Main

IPC分类号： G01F23/26 ,  G01N27/22 ,  G01N33/28 ,  G01R27/26 ,  B60Q1/00

CPC分类号： G01R27/2605 ,  G01N27/223 ,  G01N33/2847

摘要： A reference capacitor is coupled in parallel with a capacitor of which the size thereof is variable and an oscillator is used to alternately charge and discharge both capacitors between first and second voltage levels. The absolute magnitude of the current flowing through the reference capacitor, which varies in proportion to the size of the variable capacitor, is detected which is indicative of the variations in size of the variable capacitor. If the variable capacitor is disposed in the fuel tank of a vehicle, water in the fuel will cause the effective capacitance value of the capacitor to increase which reduces the absolute magnitude of the current that is detected. The absolute magnitude of the detected current can be utilized to indicate excessive water levels in the fuel.

摘要翻译： 参考电容器与其尺寸可变的电容器并联耦合，并且使用振荡器在第一和第二电压电平之间交替地对两个电容器进行充电和放电。 检测流过参考电容器的电流的绝对量值，其与可变电容器的尺寸成比例地变化，这表示可变电容器的尺寸变化。 如果可变电容器设置在车辆的燃料箱中，则燃料中的水将导致电容器的有效电容值增加，这降低了检测到的电流的绝对值。 检测到的电流的绝对大小可以用来表示燃料中过多的水位。

公开(公告)号：US4109214A

公开(公告)日：1978-08-22

申请号：US802170

申请日：1977-05-31

申请人： W. Eric Main

发明人： W. Eric Main

IPC分类号： H03F3/45 ,  H03G1/00 ,  H03H11/32 ,  H03H11/40 ,  H03F3/04 ,  H03G3/00

CPC分类号： H03H11/405 ,  H03F3/45071 ,  H03G1/0023 ,  H03H11/32

摘要： The disclosed unbalanced-to-balanced signal converter circuit includes two pairs of transistors, each pair having first and second transistors with the base-to-emitter junctions of each pair being connected in series between a reference potential point and a constant current source. A driver circuit is arranged to supply an unbalanced input signal which increases the conductivities of the first transistor of the first pair and the second transistor of the second pair, while decreasing the conductivities of the second transistor of the first pair and the first transistor of the second pair, and vice versa. Balanced linear output signals are provided at the collectors of the second pair of transistors. A gain controlled amplifier and a capacitance control circuit each including the unbalanced-to-balanced converter are also disclosed.