-
公开(公告)号：US10445199B2
公开(公告)日：2019-10-15
申请号：US15388883
申请日：2016-12-22
发明人： Kiran Kumar Gunnam
摘要： The present disclosure generally relates to methods for managing bad pages in storage devices. When a page is bad or faulty, a spare page is used to store the data because the bad or faulty page is unreliable for data storage. When the time comes to read the data from the bad page or write data onto the page, there needs to be some direction to the spare page. The bad or faulty page may contain a pointer to direct to the location of the spare page or metadata containing directions to the location of the spare page. A hash function may be used to calculate that the stored data in the bad or faulty page is incorrect and, once decoded, provide direction to the spare page. By using pointers, metadata or hash functions, additional data tables are unnecessary and data storage is more efficient.
-
公开(公告)号：US10452533B2
公开(公告)日：2019-10-22
申请号：US15449612
申请日：2017-03-03
发明人： Kiran Kumar Gunnam
IPC分类号： G06F12/02 , G06F12/06 , G06F12/10 , G06F7/76 , G06F12/1072
摘要： Systems and methods for determining a physical block address (PBA) of a non-volatile memory (NVM) to enable a data access of a corresponding logical block address (LBA) are described. One such method includes generating a first physical block address (PBA) candidate from a LBA using a first function; generating a second physical block address (PBA) candidate from the LBA using a second function; and selecting either the first PBA candidate or the second PBA candidate for the data access based on information related to a background swap of data stored at the first PBA candidate and a background swap of data stored at the second PBA candidate.
-
公开(公告)号：US11513950B2
公开(公告)日：2022-11-29
申请号：US17213005
申请日：2021-03-25
发明人： Kiran Kumar Gunnam
IPC分类号： G06F12/02 , G06F12/0873 , G06F3/06
摘要： A method, circuit, and system for managing wear levelling in non-volatile memory. First, an original physical block address (PBA) for a logical block address (LBA) of a write operation may be received. The original PBA is one of a set of PBAs for data blocks of a non-volatile memory array. Each of these PBAs may be uniquely mapped to a particular LBA using a multistage interconnection network (MIN). A swap PBA may next be determined for the LBA. The swap PBA may be selected from the set of PBAs uniquely mapped using the MIN. Then, the MIN may be configured to map the LBA to the swap PBA. Finally, data of a first data block stored at the original PBA may be swapped with data of a second data block stored at the swap PBA.
-
公开(公告)号：US10725709B2
公开(公告)日：2020-07-28
申请号：US16149091
申请日：2018-10-01
发明人： Arup De , Kiran Kumar Gunnam
摘要： Systems and methods for offloading processing from a host to one or more storage processing units using an interconnect network are provided. One such method includes receiving a processing task from the host at a first storage processing unit (SPU) of a plurality of SPUs via a host interface, performing, at the first SPU, the processing task, and transferring data from the first SPU to a second SPU via an interconnection network, where each of the plurality of SPUs includes a non-volatile memory (NVM) and a processing circuitry configured to perform the processing task.
-
公开(公告)号：US10459793B2
公开(公告)日：2019-10-29
申请号：US15073409
申请日：2016-03-17
摘要： A data storage device may include a non-volatile memory array and a controller. The non-volatile memory array may include a plurality of dies. Each die of the plurality of data dies may include a plurality of words, where a word is an access unit of a die. The controller may be configured to store user data to a respective first word of at least a first die and a second die of the plurality of data dies. A page of user data may include the user data stored at the respective first words of the at least first die and second die. The controller may also be configured to store parity data to a first portion of a first word of a third die. The controller may be further configured to store metadata to a second portion of the first word of the third die.
-
6.发明申请公开(公告)号：US20190034090A1
公开(公告)日：2019-01-31
申请号：US16149091
申请日：2018-10-01
发明人： Arup De , Kiran Kumar Gunnam
CPC分类号： G06F3/067 , G06F3/0613 , G06F3/0647 , G06F9/5033 , G06F2209/509
摘要： Systems and methods for offloading processing from a host to one or more storage processing units using an interconnect network are provided. One such method includes receiving a processing task from the host at a first storage processing unit (SPU) of a plurality of SPUs via a host interface, performing, at the first SPU, the processing task, and transferring data from the first SPU to a second SPU via an interconnection network, where each of the plurality of SPUs includes a non-volatile memory (NVM) and a processing circuitry configured to perform the processing task.
-
公开(公告)号：US10175890B2
公开(公告)日：2019-01-08
申请号：US15388623
申请日：2016-12-22
摘要： The present disclosure generally relates to methods of reading data from a memory device using non-binary ECCs. The memory device includes multiple memory cells where each memory cell has multiple pages that are arranged in distinct layouts for physical addresses thereof. When a read request is received from a host device to obtain data from a specific page of a specific memory cell of a memory device, rather than reading the data from all pages of the memory cell, the data can be read from just the desired page and then decoded. Following decoding, the data can be delivered to the host device. Because only the data from a specific page of a memory cell is read, rather than the entire memory cell, the read latency is reduced when compared to reading the entire memory cell.
-
公开(公告)号：US20170293555A1
公开(公告)日：2017-10-12
申请号：US15627042
申请日：2017-06-19
发明人： Kiran Kumar Gunnam
CPC分类号： G06F12/0607 , G06F12/0246 , G06F2212/1016 , G06F2212/1044 , G06F2212/214 , G06F2212/7201 , G06F2212/7211
摘要： Systems and methods for determining a cumulative control state for mapping logical block addresses (LBAs) to physical block addresses (PBAs) are disclosed. One such system includes a bitonic network including first switches and configured to receive a first randomly ordered list and random switch settings, determine a permutation of the first randomly ordered list using the random switch settings at the first switches, where the permutation includes a second randomly ordered list, and output the second randomly ordered list; a bitonic sorter including second switches and configured to receive the second randomly ordered list, sort the second randomly ordered list, and output settings of the second switches used to achieve the sort, where the second switch settings define a cumulative control state; and an access network configured to determine a PBA of a non-volatile memory (NVM) to enable a data access of a corresponding LBA using the cumulative control state.
-
公开(公告)号：US10452560B2
公开(公告)日：2019-10-22
申请号：US15627091
申请日：2017-06-19
发明人： Kiran Kumar Gunnam
IPC分类号： G06F12/1072 , G06F12/02 , G06F7/76 , G06F12/06
摘要： Systems and methods for wear leveling in non-volatile memories (NVMs) are disclosed. One such system includes a cumulative control state determiner configured to determine a cumulative control state indicative of a state of random mappings between physical block addresses (PBAs) and logical block addresses (LBAs) of an NVM, an access network configured to translate a LBA to a PBA based on the cumulative control state, and a background swap scheduler configured to swap PBAs assigned to preselected LBAs based on a control state. One such method involves determining a cumulative control state indicative of a state of random mappings between physical block addresses (PBAs) and logical block addresses (LBAs) of an NVM, translating a LBA to a PBA based on the cumulative control state, and swapping PBAs assigned to preselected LBAs based on a control state.
-
公开(公告)号：US10445232B2
公开(公告)日：2019-10-15
申请号：US15627042
申请日：2017-06-19
发明人： Kiran Kumar Gunnam
摘要： Systems and methods for determining a cumulative control state for mapping logical block addresses (LBAs) to physical block addresses (PBAs) are disclosed. One such system includes a bitonic network including first switches and configured to receive a first randomly ordered list and random switch settings, determine a permutation of the first randomly ordered list using the random switch settings at the first switches, where the permutation includes a second randomly ordered list, and output the second randomly ordered list; a bitonic sorter including second switches and configured to receive the second randomly ordered list, sort the second randomly ordered list, and output settings of the second switches used to achieve the sort, where the second switch settings define a cumulative control state; and an access network configured to determine a PBA of a non-volatile memory (NVM) to enable a data access of a corresponding LBA using the cumulative control state.
-
-
-
-
-
-
-
-
-
搜索结果
19 条记录 (耗时 0.027 秒)
