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公开(公告)号：US20240170056A1
公开(公告)日：2024-05-23
申请号：US18354178
申请日：2023-07-18
发明人： Minghai Qin , Chao Sun , Dejan Vucinic , Henry Yip , Jonas Goode , Richard Galbraith , Iouri Oboukhov
IPC分类号： G11C11/54 , G11C11/416
CPC分类号： G11C11/54 , G11C11/416
摘要： Example channel circuits, data storage devices, and methods for using a trained neural network to estimate the noise mixture in a read signal are described. Samples are determined from a digital read signal, such as the read signal from the non-volatile storage medium of a data storage device. The samples are processed through one or more instances of a neural network comprised of trained coefficients and outputting a set of estimate values for a noise mixture of the read signal. The set of estimate values may then be used to adjust parameters of the read channel for processing the read signal to detect and decode data.
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公开(公告)号：US20210334338A1
公开(公告)日：2021-10-28
申请号：US17370716
申请日：2021-07-08
发明人： Wen Ma , Pi-Feng Chiu , Minghai Qin , Won Ho Choi , Martin Lueker-Boden
摘要： An innovative low-bit-width device may include a first digital-to-analog converter (DAC), a second DAC, a plurality of non-volatile memory (NVM) weight arrays, one or more analog-to-digital converters (ADCs), and a neural circuit. The first DAC is configured to convert a digital input signal into an analog input signal. The second DAC is configured to convert a digital previous hidden state (PHS) signal into an analog PHS signal. NVM weight arrays are configured to compute vector matrix multiplication (VMM) arrays based on the analog input signal and the analog PHS signal. The NVM weight arrays are coupled to the first DAC and the second DAC. The one or more ADCs are coupled to the plurality of NVM weight arrays and are configured to convert the VMM arrays into digital VMM values. The neural circuit is configured to process the digital VMM values into a new hidden state.
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公开(公告)号：US20240193088A1
公开(公告)日：2024-06-13
申请号：US18231730
申请日：2023-08-08
发明人： Chao Sun , Qingbo Wang , Minghai Qin , Jaco Hofmann , Anand Kulkarni , Dejan Vucinic , Zvonimir Bandic
IPC分类号： G06F12/0862 , G06N20/00
CPC分类号： G06F12/0862 , G06N20/00
摘要： A memory device includes a first memory and a second memory that caches data stored in the first memory. At least one controller of the memory device receives page fault information from a host. The page fault information results from a request for data by the host that is stored in the first memory but is not cached in the second memory when requested by the host. The memory device uses the received page fault information for one or more inputs into a prefetch model trained by Machine Learning (ML) to generate at least one inference. Based at least in part on the at least one inference, prefetch data is cached in the second memory. In one aspect, the page fault information is used to train the prefetch model. In another aspect, the page fault information includes at least one virtual address used by the host for the requested data.
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公开(公告)号：US11251812B2
公开(公告)日：2022-02-15
申请号：US16909815
申请日：2020-06-23
发明人： Minghai Qin
IPC分类号： H03M13/00 , H03M13/19 , H03M13/25 , G06F11/10 , G11C29/52 , H03M7/24 , H03M13/05 , G11C13/00 , G11C29/04
摘要： Systems and methods for dynamically encoding and decoding binary numbers using linear-time algorithms that encode and decode Hamming Distance-Based representations for the binary numbers are described. The binary numbers may correspond with integer values, such as 64-bit, 128-bit, or 256-bit integer values. In some cases, in response to detecting that a binary number is to be stored using a particular type of memory (e.g., a phase change memory), the binary number may first be encoded using a Hamming Distance-Based representation and then the encoded data may be written to the particular type of memory. The binary number may be encoded by generating a binary string or a binary array representing the binary number such that if one bit flips within the binary string or the binary array, the maximum distortion in the number is less than a threshold amount (e.g., less than 256).
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公开(公告)号：US10373528B2
公开(公告)日：2019-08-06
申请号：US15379216
申请日：2016-12-14
摘要： The present disclosure generally relates to a method of burning a file in a memory device after the file has been read. Once a file has been read, an algorithm uses the memory device to create errors that the error correction code (ECC) cannot decode the error. In creating the error, the entire word line is destroyed physically rather than logically so that retrieving information from that particular word line is no longer possible. In creating the error, adjacent word lines are not affected. The error renders the file burned.
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公开(公告)号：US10360973B2
公开(公告)日：2019-07-23
申请号：US15472326
申请日：2017-03-29
摘要： In this disclosure, data mapping based on three dimensional lattices that have an improved sum rate (i.e., lifetime capacity) with low read latency is disclosed. During the write, a memory location is written to multiple times prior to erasure. Specifically, for the first write, there are 4/3 bits per cell available for writing, which is about 10.67 kB per cell are used for data storage. Then, for the second write, there is one bit per cell, which is 8 kB per cell for data storage. If considering a block with 128 different cells and writing 32 kB of data, the first write results in 42.66 data writes while the second write results in 32 writes for a total of 74.66 writes. Previously, the number of writes for 32 kB would be 64 writes. Thus, by writing twice prior to erasure, more data can be stored.
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公开(公告)号：US20190215014A1
公开(公告)日：2019-07-11
申请号：US15933697
申请日：2018-03-23
发明人： Minghai Qin
摘要： Systems and methods for dynamically encoding and decoding binary numbers using linear-time algorithms that encode and decode Hamming Distance-Based representations for the binary numbers are described. The binary numbers may correspond with integer values, such as 64-bit, 128-bit, or 256-bit integer values. In some cases, in response to detecting that a binary number is to be stored using a particular type of memory (e.g., a phase change memory), the binary number may first be encoded using a Hamming Distance-Based representation and then the encoded data may be written to the particular type of memory. The binary number may be encoded by generating a binary string or a binary array representing the binary number such that if one bit flips within the binary string or the binary array, the maximum distortion in the number is less than a threshold amount (e.g., less than 256).
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公开(公告)号：US10175890B2
公开(公告)日：2019-01-08
申请号：US15388623
申请日：2016-12-22
摘要： The present disclosure generally relates to methods of reading data from a memory device using non-binary ECCs. The memory device includes multiple memory cells where each memory cell has multiple pages that are arranged in distinct layouts for physical addresses thereof. When a read request is received from a host device to obtain data from a specific page of a specific memory cell of a memory device, rather than reading the data from all pages of the memory cell, the data can be read from just the desired page and then decoded. Following decoding, the data can be delivered to the host device. Because only the data from a specific page of a memory cell is read, rather than the entire memory cell, the read latency is reduced when compared to reading the entire memory cell.
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9.发明申请公开(公告)号：US20180181301A1
公开(公告)日：2018-06-28
申请号：US15388737
申请日：2016-12-22
发明人： Zvonimir Z. Bandic , Minghai Qin , Seung-Hwan Song
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483
摘要： Aspects of the disclosure provide a method and a data storage apparatus for storing fractional bits per cell with low-latency read per page. In various embodiments, the memory cells are configured to store a fractional number of bits per cell using a multi-page construction with reduced number of read per page as compared to a single page construction. The data storage apparatus store data in a plurality of non-volatile memory (NVM) cells configured to store information in a plurality of pages, wherein each of the NVM cells is programmable to one of L program states for representing a fractional number of bits. The data storage apparatus reads a first part of the data from a first page of the plurality of pages by applying M number of read voltages to the plurality of NVM cells, wherein the M number of read voltages is less than L−1 program states.
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公开(公告)号：US09912352B1
公开(公告)日：2018-03-06
申请号：US15614914
申请日：2017-06-06
发明人： Minghai Qin , Chao Sun , Dejan Vucinic
CPC分类号： H03M7/6035 , H03M7/02 , H03M7/24 , H03M13/00
摘要： Technology is described herein for encoding and decoding numbers. In one aspect, floating point numbers are represented as binary strings. The binary strings may be encoded in a manner such that if one bit flips, the average and maximum distortion in the number that is represented by the binary string is relatively small. In one aspect, 2^n binary strings are ordered across an interval [a, b) in accordance with their Hamming weights. Numbers in the interval may be uniformly quantized into one of 2^n sub-intervals. For example, floating point numbers in the interval [a, b) may be uniformly quantized into 2^n sub-intervals. These 2^n sub-intervals may be mapped to the 2^n binary strings. Thus, the number may be assigned to one of the 2^n binary strings. Doing so may reduce the distortion in the number in the event that there is a bit flip in the assigned binary string.
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