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公开(公告)号：US11165717B2
公开(公告)日：2021-11-02
申请号：US14922547
申请日：2015-10-26
发明人： Zvonimir Z. Bandic , Luis Cargnini , Dejan Vucinic
IPC分类号： G06F13/18 , H04L12/933 , H04L12/741 , H04L12/707 , G06F3/06
摘要： Embodiments disclosed herein generally relate to the use of Network-on-Chip architecture for solid state memory structures, both volatile and non-volatile, which provide for the access of memory storage blocks via a router. As such, data may be sent to and/or from the memory storage blocks as data packets on the chip. The Network-on-Chip architecture may further be utilized to interconnect unlimited numbers of memory cell matrices, spread on a die, thus allowing for reduced latencies among matrices, selective power control, unlimited memory density growth without major latency penalties, and reduced parasitic capacitance and resistance. Other benefits may include improved signal integrity, larger die areas available to implement memory arrays, and higher frequency of operation.
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公开(公告)号：US10275175B2
公开(公告)日：2019-04-30
申请号：US14507572
申请日：2014-10-06
摘要： Techniques for providing file system functionality over a PCIe interface are disclosed. In some embodiments, the techniques may be realized as a method for providing file system functionality over a PCIe interface including receiving from a host device a storage command, specially devised for such a standard protocol, at a PCIe-based device controller, parsing, using at least one computer processor of the PCIe-based device controller, the storage command, traversing, using PCIe-based device controller, one or more portions of file system metadata of an associated storage media device, wherein the PCIe-based device controller is configured to traverse the one or more portions of file system metadata based on the parsed storage command independent of any subsequent communication with the host device, and returning data to the host device.
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公开(公告)号：US10157656B2
公开(公告)日：2018-12-18
申请号：US14834743
申请日：2015-08-25
发明人： Zvonimir Z. Bandic , Jeffery Robinson Childress , Luiz M. Franca-Neto , Jordan Asher Katine , Neil Leslie Robertson
摘要： A magnetic memory cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M1, and a second conductor M2 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M1, M2 is formed of a magnetic material, and the conductor M2 is more conductive than conductor M1. Steering of current is provided for programming the magnetic memory cell.
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公开(公告)号：US10049076B2
公开(公告)日：2018-08-14
申请号：US15090249
申请日：2016-04-04
发明人： Dejan Vucinic , Zvonimir Z. Bandic
摘要： The present disclosure relates to methods and systems for implementing a high-speed serial bus with inhomogeneous lane bundles and encodings. A system for transmitting information can include a bus with a plurality of lanes and a host in communication with a target. The host can run an application that writes data to and reads data from storage. The host can assign a first plurality of lanes and a first encoding to a first bundle and assign a second plurality of lanes and a second encoding to a second bundle. The host can also evaluate a bandwidth requirement for the read and write instructions and evaluate a bus performance. The host can also regroup the first bundle or the second bundle based on bandwidth requirements and bus performance and can assign a third plurality of lanes and a third encoding to the at least one of the first bundle and the second bundle.
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公开(公告)号：US09911494B1
公开(公告)日：2018-03-06
申请号：US15403800
申请日：2017-01-11
发明人： Zvonimir Z. Bandic , Won Ho Choi , Jay Kumar
CPC分类号： G11C13/0069 , G11C13/0097
摘要： A storage device includes an interface, NVM device, and control module. The control module may be configured to receive a first write operation and a second write operation. The first write operation comprises a SET operation configured to place a cell of the NVM device in a relatively low-resistance state. The control module may be further configured to execute the first write operation by causing an electrical pulse to be applied to a first cell of the NVM device to place the first cell in the relatively low-resistance state. The control module may be further configured to execute the second write operation by causing an electrical pulse to be applied to a second cell of the NVM device before the first electrical pulse has concluded. A single tile of the NVM device includes the first cell and the second cell.
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公开(公告)号：US20180024751A1
公开(公告)日：2018-01-25
申请号：US15214386
申请日：2016-07-19
发明人： Zvonimir Z. Bandic , Jing Shi Booth , Sanghoon Chu , Cyril Guyot , Robert E. Mateescu , Minghai Qin , Qingbo Wang
IPC分类号： G06F3/06
CPC分类号： G06F3/0688 , G06F3/061 , G06F3/064
摘要： A storage device may include a data storage portion including a set of blocks designated to store metadata and a controller. The controller may be configured to write first metadata at a first location designated by a first pointer. The first location may reference a block that does not contain any valid metadata. The controller may be configured to determine a number of valid blocks of previously written metadata in a subset of the set of blocks. A first block of the subset may be at a second location designated by a second pointer. The controller may be configured to, if the number of valid blocks is greater than zero, rewrite the valid previously written metadata to a group of one or more sequential blocks.
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公开(公告)号：US09830219B2
公开(公告)日：2017-11-28
申请号：US14627580
申请日：2015-02-20
CPC分类号： G06F11/1068 , G06F11/1072 , G11C11/5628 , G11C16/00 , G11C29/44 , G11C29/52 , G11C2029/0409
摘要： Techniques for encoding data for non-volatile memory storage systems are disclosed. In one particular embodiment, the techniques may be realized as a method including writing first data to the memory, reading the first data from the memory, analyzing the first read data such that the analyzing includes determining whether the read data includes an error, encoding second data based on the analyzing of the first data such that the second data is encoded to be written to a position adjacent to the error when it is determined that the read data includes the error, and writing the encoded second data to the memory at the position.
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公开(公告)号：US09778859B2
公开(公告)日：2017-10-03
申请号：US14631187
申请日：2015-02-25
发明人： Dejan Vucinic , Zvonimir Z. Bandic , Cyril Guyot , Robert Mateescu , Qingbo Wang
CPC分类号： G06F3/0613 , G06F3/0659 , G06F3/0661 , G06F3/0679 , G06F12/08 , G06F2206/1014
摘要： The present disclosure relates to methods and systems for performing operations in a communications protocol. An example method can include submitting, from a device, a request for a queue entry representing a command from a host comprising a request for data stored at a device memory location; receiving the command from the host; and executing the command. An example method can also include selecting a bit string representing whether a requested data stream has been received, and storing the bit string into a memory buffer portion to mark the buffer portion. The method can include receiving, into the memory buffer, the stream. The method can include retrieving contents of the buffer portion, and determining whether the contents contain the bit string. If so, the method can include determining that portions of the stream have not been received. Otherwise, the method can include determining that the stream has been received.
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公开(公告)号：US20170269992A1
公开(公告)日：2017-09-21
申请号：US15073409
申请日：2016-03-17
CPC分类号： G06F11/108 , G06F11/1048 , G11C29/52
摘要： A data storage device may include a non-volatile memory array and a controller. The non-volatile memory array may include a plurality of dies. Each die of the plurality of data dies may include a plurality of words, where a word is an access unit of a die. The controller may be configured to store user data to a respective first word of at least a first die and a second die of the plurality of data dies. A page of user data may include the user data stored at the respective first words of the at least first die and second die. The controller may also be configured to store parity data to a first portion of a first word of a third die. The controller may be further configured to store metadata to a second portion of the first word of the third die.
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公开(公告)号：US11546272B2
公开(公告)日：2023-01-03
申请号：US17486528
申请日：2021-09-27
发明人： Zvonimir Z. Bandic , Luis Cargnini , Dejan Vucinic
IPC分类号： G06F13/18 , H04L49/109 , H04L45/74 , H04L45/00 , G06F3/06
摘要： Embodiments disclosed herein generally relate to the use of Network-on-Chip architecture for solid state memory structures which provide for the access of memory storage blocks via a router. As such, data may be sent to and/or from the memory storage blocks as data packets on the chip. The Network-on-Chip architecture may further be utilized to interconnect unlimited numbers of memory cell matrices, spread on a die, thus allowing for reduced latencies among matrices, selective power control, unlimited memory density growth without major latency penalties, and reduced parasitic capacitance and resistance. Other benefits may include improved signal integrity, larger die areas available to implement memory arrays, and higher frequency of operation.
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