公开(公告)号：US11031435B2

公开(公告)日：2021-06-08

申请号：US16442858

申请日：2019-06-17

申请人： Western Digital Technologies, Inc.

发明人： Michael Grobis ,  Joyeeta Nag ,  Derek Stewart

IPC分类号： H01L27/24 ,  H01F10/32 ,  H01L45/00 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

摘要： A memory device includes a plurality of memory cells, and an isolation material portion located between the memory cells. The isolation material portion includes at least one ovonic threshold switch material portion.

公开(公告)号：US10777248B1

公开(公告)日：2020-09-15

申请号：US16459389

申请日：2019-07-01

申请人： WESTERN DIGITAL TECHNOLOGIES, INC.

发明人： Goran Mihajlovic ,  Neil Smith ,  Michael Grobis ,  Michael Tran

IPC分类号： G11C11/16 ,  H01F10/32 ,  H01L27/22 ,  H01L43/02

摘要： A magnetoresistive random access memory (MRAM) memory cell comprises a pinned layer having fixed direction of magnetization that is perpendicular to a plane of the pinned layer, a first free layer having a direction of magnetization that can be switched and is perpendicular to a plane of the first free layer, a tunnel barrier positioned between the pinned layer and the first free layer, a second free layer having a direction of magnetization that can be switched, and a spacer layer positioned between the first free layer and the second free layer. Temperature dependence of coercivity of the second free layer is greater than temperature dependence of coercivity of the first free layer.

公开(公告)号：US11271040B1

公开(公告)日：2022-03-08

申请号：US17075980

申请日：2020-10-21

申请人： WESTERN DIGITAL TECHNOLOGIES, INC.

发明人： Derek Stewart ,  John Read ,  Michael Grobis

IPC分类号： H01L27/24 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L45/00 ,  H01L43/12 ,  G11C13/00

摘要： A memory cell includes an ovonic threshold switch (OTS) selector containing a first electrode, a second electrode, an OTS located between the first electrode and the second electrode, and a current focusing layer containing discrete electrically conductive current focusing regions having a width of 30 nm or less located between the first electrode and the OTS, and a memory device located in electrical series with the OTS selector.

公开(公告)号：US10891999B1

公开(公告)日：2021-01-12

申请号：US16458651

申请日：2019-07-01

申请人： WESTERN DIGITAL TECHNOLOGIES, INC.

发明人： Goran Mihajlovic ,  Michael Grobis

IPC分类号： G11C11/16 ,  H01L43/08 ,  H01L43/06

摘要： A MRAM memory cell comprises a SHE layer, a magnetic bit layer with perpendicular anisotropy and an Oersted layer. The magnetic bit layer has a switchable direction of magnetization in order to store data. Data is written to the MRAM memory cell using the Spin Hall Effect so that spin current generated in the SHE layer exerts a torque on the magnetic bit layer while the Oersted layer provides heat and an Oersted field to enable deterministic switching. Data is read form the MRAM memory cell using the Anomalous Hall Effect and sensing voltage at the Oersted layer.

公开(公告)号：US11004489B2

公开(公告)日：2021-05-11

申请号：US16459369

申请日：2019-07-01

申请人： WESTERN DIGITAL TECHNOLOGIES, INC.

发明人： Goran Mihajlovic ,  Tiffany Santos ,  Michael Grobis

IPC分类号： G11C11/00 ,  G11C11/16 ,  H01L43/10 ,  H01L43/02 ,  H01L43/08

摘要： A perpendicular spin transfer torque MRAM memory cell includes a magnetic tunnel junction stack comprising a pinned layer having a fixed direction of magnetization, a free layer having a direction of magnetization that can be switched, a tunnel barrier between the pinned layer and the free layer, a cap layer above the free layer and one or more in-stack multi-layer thermal barrier layers having multiple internal interfaces between materials. The thermal barrier layers have high enough thermal resistivity to maintain the heat generated in the memory cell and low enough electrical resistivity to not materially change the electrical resistance of the memory cell. One embodiment further includes a thermal barrier liner surrounding the free layer, pinned layer, tunnel barrier and cap layer.