利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

81 条记录 (耗时 0.033 秒)

    Methods for forming back-end-of-line resistive semiconductor structures
    2.
    发明授权
    Methods for forming back-end-of-line resistive semiconductor structures 有权
    形成后端电阻半导体结构的方法

    公开(公告)号：US07977201B2

    公开(公告)日：2011-07-12

    申请号：US12191633

    申请日：2008-08-14

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

    IPC分类号： H01L21/20

    CPC分类号： H01L23/5228 ,  H01L21/76816 ,  H01L23/5226 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In one embodiment, a second metal line embedded in a second dielectric layer overlies a first metal line embedded in a first dielectric layer. A portion of the second dielectric layer overlying the first metal line is recessed employing a photoresist and the second metal line as an etch mask. A doped semiconductor spacer is formed within the recess to provide a resistive link between the first metal line and the second metal line. In another embodiment, a first metal line and a second metal line are embedded in a dielectric layer. An area of the dielectric layer laterally abutting the first and second metal lines is recessed employing a photoresist and the first and second metal lines as an etch mask. A doped semiconductor spacer is formed on sidewalls of the first and second metal lines, providing a resistive link between the first and second metal lines.

    摘要翻译： 在一个实施例中，嵌入在第二介电层中的第二金属线覆盖在嵌入第一介电层中的第一金属线上。 覆盖第一金属线的第二电介质层的一部分是使用光致抗蚀剂凹陷的，而第二金属线作为蚀刻掩模。 在凹槽内形成掺杂半导体衬垫，以在第一金属线和第二金属线之间提供电阻连接。 在另一个实施例中，第一金属线和第二金属线嵌入在电介质层中。 使用光致抗蚀剂和第一和第二金属线作为蚀刻掩模来凹入与第一和第二金属线横向邻接的电介质层的区域。 掺杂半导体衬垫形成在第一和第二金属线的侧壁上，提供第一和第二金属线之间的电阻连接。

    Device structures for a memory cell of a non-volatile random access memory and design structures for a non-volatile random access memory
    3.
    发明授权
    Device structures for a memory cell of a non-volatile random access memory and design structures for a non-volatile random access memory 失效
    用于非易失性随机存取存储器的存储器单元的装置结构和用于非易失性随机存取存储器的设计结构

    公开(公告)号：US07804124B2

    公开(公告)日：2010-09-28

    申请号：US12118241

    申请日：2008-05-09

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    IPC分类号： H01L29/788

    CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L29/42324

    摘要： Device and design structures for memory cells in a non-volatile random access memory (NVRAM). The device structure includes a semiconductor body in direct contact with the insulating layer, a control gate electrode, and a floating gate electrode in direct contact with the insulating layer. The semiconductor body includes a source, a drain, and a channel between the source and the drain. The floating gate electrode is juxtaposed with the channel of the semiconductor body and is disposed between the control gate electrode and the insulating layer. A first dielectric layer is disposed between the channel of the semiconductor body and the floating gate electrode. A second dielectric layer is disposed between the control gate electrode and the floating gate electrode.

    摘要翻译： 非易失性随机存取存储器（NVRAM）中存储单元的器件和设计结构。 器件结构包括与绝缘层直接接触的半导体本体，控制栅电极和与绝缘层直接接触的浮栅电极。 半导体本体包括源极，漏极以及源极和漏极之间的沟道。 浮置栅电极与半导体本体的沟道并置并且设置在控制栅电极和绝缘层之间。 第一电介质层设置在半导体本体的沟道和浮栅之间。 第二介电层设置在控制栅电极和浮栅电极之间。

    Methods For Forming Back-End-Of-Line Resistive Semiconductor Structures
    4.
    发明申请
    Methods For Forming Back-End-Of-Line Resistive Semiconductor Structures 有权
    形成后端电阻半导体结构的方法

    公开(公告)号：US20100041202A1

    公开(公告)日：2010-02-18

    申请号：US12191633

    申请日：2008-08-14

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

    IPC分类号： H01L21/02

    CPC分类号： H01L23/5228 ,  H01L21/76816 ,  H01L23/5226 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In one embodiment, a second metal line embedded in a second dielectric layer overlies a first metal line embedded in a first dielectric layer. A portion of the second dielectric layer overlying the first metal line is recessed employing a photoresist and the second metal line as an etch mask. A doped semiconductor spacer is formed within the recess to provide a resistive link between the first metal line and the second metal line. In another embodiment, a first metal line and a second metal line are embedded in a dielectric layer. An area of the dielectric layer laterally abutting the first and second metal lines is recessed employing a photoresist and the first and second metal lines as an etch mask. A doped semiconductor spacer is formed on sidewalls of the first and second metal lines, providing a resistive link between the first and second metal lines.

    摘要翻译： 在一个实施例中，嵌入在第二介电层中的第二金属线覆盖在嵌入第一介电层中的第一金属线上。 覆盖第一金属线的第二电介质层的一部分使用光致抗蚀剂凹陷，第二金属线作为蚀刻掩模。 在凹槽内形成掺杂半导体衬垫，以在第一金属线和第二金属线之间提供电阻连接。 在另一个实施例中，第一金属线和第二金属线嵌入在电介质层中。 使用光致抗蚀剂和第一和第二金属线作为蚀刻掩模来凹入与第一和第二金属线横向邻接的电介质层的区域。 掺杂半导体衬垫形成在第一和第二金属线的侧壁上，提供第一和第二金属线之间的电阻连接。

    BACK-END-OF-LINE RESISTIVE SEMICONDUCTOR STRUCTURES
    7.
    发明申请
    BACK-END-OF-LINE RESISTIVE SEMICONDUCTOR STRUCTURES 审中-公开
    后端电阻半导体结构

    公开(公告)号：US20110161896A1

    公开(公告)日：2011-06-30

    申请号：US13042947

    申请日：2011-03-08

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

    IPC分类号： G06F17/50

    CPC分类号： H01L27/115 ,  H01L23/5256 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewalls of the second metal line and vertically abutting a top surface of the first metal line provides a resistive link between the first and second metal lines. In another embodiment, another BEOL resistive structure comprises a first metal line and a second metal line are embedded in a dielectric layer. A doped semiconductor spacer or plug laterally abutting the sidewalls of the first and second metal lines provides a resistive link between the first and second metal lines.

    摘要翻译： 在一个实施例中，后端行（BEOL）电阻结构包括嵌入在第二电介质层中的第二金属线，并且覆盖嵌入在第一介电层中的第一金属线。 横向邻接第二金属线的侧壁并垂直邻接第一金属线的顶表面的掺杂半导体间隔物或插塞提供第一和第二金属线之间的电阻连接。 在另一个实施例中，另一个BEOL电阻结构包括第一金属线，第二金属线嵌入电介质层。 横向邻接第一和第二金属线的侧壁的掺杂半导体间隔件或插塞提供第一和第二金属线之间的电阻连接。

    Back-end-of-line resistive semiconductor structures
    8.
    发明授权
    Back-end-of-line resistive semiconductor structures 有权
    后端电阻半导体结构

    公开(公告)号：US07939911B2

    公开(公告)日：2011-05-10

    申请号：US12191683

    申请日：2008-08-14

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

    IPC分类号： H01L29/00

    CPC分类号： H01L27/115 ,  H01L23/5256 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewalls of the second metal line and vertically abutting a top surface of the first metal line provides a resistive link between the first and second metal lines. In another embodiment, another BEOL resistive structure comprises a first metal line and a second metal line are embedded in a dielectric layer. A doped semiconductor spacer or plug laterally abutting the sidewalls of the first and second metal lines provides a resistive link between the first and second metal lines.

    摘要翻译： 在一个实施例中，后端行（BEOL）电阻结构包括嵌入在第二电介质层中的第二金属线，并且覆盖嵌入在第一介电层中的第一金属线。 横向邻接第二金属线的侧壁并垂直邻接第一金属线的顶表面的掺杂半导体间隔物或插塞提供第一和第二金属线之间的电阻连接。 在另一个实施例中，另一个BEOL电阻结构包括第一金属线，第二金属线嵌入电介质层。 横向邻接第一和第二金属线的侧壁的掺杂半导体间隔件或插塞提供第一和第二金属线之间的电阻连接。

    Device structures for a metal-oxide-semiconductor field effect transistor and methods of fabricating such device structures
    9.
    发明授权
    Device structures for a metal-oxide-semiconductor field effect transistor and methods of fabricating such device structures 失效
    金属氧化物半导体场效应晶体管的器件结构及其制造方法

    公开(公告)号：US07790543B2

    公开(公告)日：2010-09-07

    申请号：US11972941

    申请日：2008-01-11

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795

    摘要： Device structures for a metal-oxide-semiconductor field effect transistor (MOSFET) that is suitable for operation at relatively high voltages and methods of forming same. The MOSFET, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a channel in a semiconductor body that is self-aligned with a gate electrode. The gate electrode and semiconductor body, which are both formed from the monocrystalline SOI layer of the SOI substrate, are separated by a gap that is filled by a gate dielectric layer. The gate dielectric layer may be composed of thermal oxide layers grown on adjacent sidewalls of the semiconductor body and gate electrode, in combination with an optional deposited dielectric material that fills the remaining gap between the thermal oxide layers.

    摘要翻译： 适用于在较高电压下工作的金属氧化物半导体场效应晶体管（MOSFET）的器件结构及其形成方法。 使用绝缘体上半导体（SOI）衬底形成的MOSFET包括半导体本体中与栅电极自对准的沟道。 由SOI衬底的单晶SOI层形成的栅电极和半导体本体由被栅极电介质层填充的间隙分开。 栅极电介质层可以由在半导体主体和栅电极的相邻侧壁上生长的热氧化物层组合，并与填充热氧化物层之间的剩余间隙的任选沉积的电介质材料组合。

    Device and design structures for memory cells in a non-volatile random access memory and methods of fabricating such device structures
    10.
    发明授权
    Device and design structures for memory cells in a non-volatile random access memory and methods of fabricating such device structures 失效
    用于非易失性随机存取存储器中的存储器单元的装置和设计结构以及制造这种器件结构的方法

    公开(公告)号：US07790524B2

    公开(公告)日：2010-09-07

    申请号：US11972949

    申请日：2008-01-11

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    IPC分类号： H01L21/00

    CPC分类号： H01L29/7881 ,  H01L29/66825

    摘要： Device and design structures for memory cells in a non-volatile random access memory (NVRAM) and methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes. The device structure, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a floating gate electrode, a semiconductor body, and a control gate electrode separated from the semiconductor body by the floating gate electrode. The floating gate electrode, the control gate electrode, and the semiconductor body, which are both formed from the monocrystalline SOI layer of the SOI substrate, are respectively separated by dielectric layers. The dielectric layers may each be composed of thermal oxide layers grown on confronting sidewalls of the semiconductor body, the floating gate electrode, and the control gate electrode. An optional deposited dielectric material may fill any remaining gap between either pair of the thermal oxide layers.

    摘要翻译： 用于非易失性随机存取存储器（NVRAM）中的存储器单元的装置和设计结构以及使用互补金属氧化物半导体（CMOS）工艺制造这种器件结构的方法。 使用绝缘体上半导体（SOI）衬底形成的器件结构包括通过浮栅电极与半导体本体分离的浮栅电极，半导体本体和控制栅电极。 由SOI衬底的单晶SOI层形成的浮置栅电极，控制栅电极和半导体本体分别由电介质层分离。 介电层可以各自由在半导体本体，浮栅电极和控制栅电极的相对侧壁上生长的热氧化物层组成。 任选沉积的介电材料可以填充任何一对热氧化物层之间的剩余间隙。