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公开(公告)号：US20070299899A1
公开(公告)日：2007-12-27
申请号：US11476329
申请日：2006-06-27
IPC分类号： G06F7/52
CPC分类号： G06F7/5324
摘要： Techniques are described to multiply two numbers, A and B. In general, multiplication is performed by using Karatsuba multiplication on the segments of A and B and adjusting the Karatsuba multiplication based on the values of the most significant bits of A and B.
摘要翻译： 技术被描述为将两个数字A和B相乘。通常，通过对A和B的段使用Karatsuba乘法来执行乘法，并且基于A和B的最高有效位的值来调整Karatsuba乘法。
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公开(公告)号：US07930337B2
公开(公告)日：2011-04-19
申请号：US11476329
申请日：2006-06-27
IPC分类号： G06F7/52
CPC分类号： G06F7/5324
摘要： Techniques are described to multiply two numbers, A and B. In general, multiplication is performed by using Karatsuba multiplication on the segments of A and B and adjusting the Karatsuba multiplication based on the values of the most significant bits of A and B.
摘要翻译： 技术被描述为将两个数字A和B相乘。通常，通过对A和B的段使用Karatsuba乘法来执行乘法，并且基于A和B的最高有效位的值来调整Karatsuba乘法。
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公开(公告)号：US08073892B2
公开(公告)日：2011-12-06
申请号：US11323994
申请日：2005-12-30
申请人： Wajdi K. Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel R. Cutter , Vinodh Gopal , Gunnar Gaubatz
发明人： Wajdi K. Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel R. Cutter , Vinodh Gopal , Gunnar Gaubatz
IPC分类号： G06F7/52
CPC分类号： G06F7/5275
摘要： In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.
摘要翻译： 通常，在一个方面，本发明描述了一种乘法器，其包括并行配置的一组多个乘法器，其中多个乘法器的组具有访问第一操作数和第二操作数以乘以具有多个段的第一操作数和第二操作数 具有多个段的操作数。 所述乘法器还包括逻辑以将所述第二操作数的单个段重复地提供给所述多个乘法器集合的每个乘法器，并且将所述第一操作数的多个相应段提供给所述多个乘法器组中的相应一个，直到所述第二 操作数已被提供给第一个操作数的每个段。 该逻辑至少部分地基于第一操作数内的相应段的位置来移动多个乘法器中的不同乘法器的输出。 乘法器还包括耦合到逻辑的累加器。
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公开(公告)号：US20070297601A1
公开(公告)日：2007-12-27
申请号：US11476432
申请日：2006-06-27
IPC分类号： H04L9/28
CPC分类号： G06F7/72
摘要： Techniques are described to determine N mod M, where N is a number having a width of n-bits, and M is a number having a width of m-bits. The techniques, generally, involve determining N′=NH2f mod M+NL and, subsequently, determining N′ mod M
摘要翻译： 描述技术来确定N mod M，其中N是具有n位宽度的数，M是具有m位宽度的数。 这些技术通常涉及确定N'= N H 2 H 2 mod M + N L L，并且随后确定N'mod M
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公开(公告)号：US20110264720A1
公开(公告)日：2011-10-27
申请号：US11323994
申请日：2005-12-30
申请人： Wajdi Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel R. Cutter , Vinodh Gopal , Gunnar Gaubatz
发明人： Wajdi Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel R. Cutter , Vinodh Gopal , Gunnar Gaubatz
CPC分类号： G06F7/5275
摘要： In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.
摘要翻译： 通常，在一个方面，本发明描述了一种乘法器，其包括并行配置的一组多个乘法器，其中多个乘法器的组具有访问第一操作数和第二操作数以乘以具有多个段的第一操作数和第二操作数 具有多个段的操作数。 所述乘法器还包括逻辑以将所述第二操作数的单个段重复地提供给所述多个乘法器集合的每个乘法器，并且将所述第一操作数的多个相应段提供给所述多个乘法器组中的相应一个，直到所述第二 操作数已被提供给第一个操作数的每个段。 该逻辑至少部分地基于第一操作数内的相应段的位置来移动多个乘法器中的不同乘法器的输出。 乘法器还包括耦合到逻辑的累加器。
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6.发明授权Executing instruction for processing by ALU accessing different scope of variables using scope index automatically changed upon procedure call and exit 失效通过ALU访问使用范围索引访问不同范围的变量的执行指令在过程调用和退出时自动更改公开(公告)号：US07475229B2
公开(公告)日：2009-01-06
申请号：US11354670
申请日：2006-02-14
申请人： Wajdi K. Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel F. Cutter , Vinodh Gopal , Gunnar Gaubatz
发明人： Wajdi K. Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel F. Cutter , Vinodh Gopal , Gunnar Gaubatz
IPC分类号： G06F9/302
CPC分类号： G06F21/602
摘要： In general, in one aspect, the disclosure describes a processing unit that includes a memory, an arithmetic logic unit, and control logic having access to program instructions of a control store. The control logic includes logic to access multiple sets of variables, variables in the different sets of variables being identically referenced by instructions, associate a one of the sets of variables as the current set of variables to be used in instructions that are executed by the arithmetic logic unit, change the set of variables associated with the current set of variables in response to a procedure call or exit, and alter the value of a variable of a set of the variables other than the set of variables associated with the current set of variables in response to an instruction.
摘要翻译： 通常，在一个方面，本公开描述了一种处理单元，其包括存储器，算术逻辑单元和具有访问控制存储器的程序指令的控制逻辑。 控制逻辑包括访问多组变量的逻辑，不同变量集合中的变量由指令相同地引用，将变量集合中的一个与当前由算术执行的指令中使用的变量集合相关联 逻辑单元，响应于过程调用或退出而改变与当前变量集相关联的变量集合，并且改变一组变量的值，而不是与当前变量集合相关联的变量集合 响应一个指令。
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公开(公告)号：US08229109B2
公开(公告)日：2012-07-24
申请号：US11476432
申请日：2006-06-27
IPC分类号： G06F7/72
CPC分类号： G06F7/72
摘要： Techniques are described to determine N mod M, where N is a number having a width of n-bits, and M is a number having a width of m-bits. The techniques, generally, involve determining N′=Nrt2f mod M+NL and, subsequently, determining N′ mod M.
摘要翻译： 描述技术来确定N mod M，其中N是具有n位宽度的数，M是具有m位宽度的数。 这些技术通常涉及确定N'= Nrt2f mod M + NL，并且随后确定N'mod M.
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公开(公告)号：US07725624B2
公开(公告)日：2010-05-25
申请号：US11323993
申请日：2005-12-30
申请人： Wajdi K. Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel R. Cutter , Vinodh Gopal , Gunnar Gaubatz
发明人： Wajdi K. Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel R. Cutter , Vinodh Gopal , Gunnar Gaubatz
CPC分类号： G06F7/52 , G06F9/3001 , G06F9/3881 , G06F9/3885 , G06F21/72
摘要： In general, in one aspect, the disclosure describes a system including multiple programmable processing units, a dedicated hardware multiplier, and at least one bus connecting the multiple processing units and multiplier.
摘要翻译： 通常，在一个方面，本公开描述了包括多个可编程处理单元，专用硬件乘法器和连接多个处理单元和乘法器的至少一个总线的系统。
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公开(公告)号：US20080075278A1
公开(公告)日：2008-03-27
申请号：US11534330
申请日：2006-09-22
IPC分类号： H04L9/30
CPC分类号： H04L9/0618 , G09C1/00 , H04L2209/122
摘要： Techniques are described herein to overlay and merge any number of tables of equivalent size and structure. Bits or patterns of bits that are similar among tables may be set to a voltage value representative of respective logical ‘0’ or ‘1’. The bits that are different among the tables may be connected to either the value of a table selection signal or its inverse.
摘要翻译： 这里描述了覆盖和合并任意数目的等效大小和结构的表的技术。 可以将表中相似的比特或模式设置为表示相应的逻辑“0”或“1”的电压值。 表中不同的位可以连接到表选择信号的值或其反相。
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10.发明授权Programmable processing unit with an input buffer and output buffer configured to exclusively exchange data with either a shared memory logic or a multiplier based upon a mode instruction 有权可编程处理单元，具有输入缓冲器和输出缓冲器，其被配置为基于模式指令与共享存储器逻辑或乘法器专门交换数据公开(公告)号：US07900022B2
公开(公告)日：2011-03-01
申请号：US11354404
申请日：2006-02-14
申请人： Wajdi K. Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel F. Cutter , Vinodh Gopal
发明人： Wajdi K. Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel F. Cutter , Vinodh Gopal
IPC分类号： G06F15/16
CPC分类号： G06F9/30145 , G06F7/5324 , G06F9/3001 , G06F9/30014 , G06F9/30036 , G06F9/3004 , G06F9/383 , G06F21/602 , G06F21/72
摘要： In general, in one aspect, a processing unit includes an input buffer to store data received by the processing unit, a memory, an arithmetic logic unit coupled to the input buffer and to the memory, an output buffer; and control logic having access to a control store of program instructions, the control logic to process instructions including an instruction to transfer data from the input buffer to the memory and an instruction to cause the arithmetic logic unit to perform an operation on operands provided by at least one of the memory and the input buffer, the instruction to output results of the operation to at least one of the memory and the output buffer.
摘要翻译： 通常，在一个方面，处理单元包括：输入缓冲器，用于存储由处理单元接收的数据;存储器;耦合到输入缓冲器和存储器的算术逻辑单元;输出缓冲器; 以及具有访问程序指令的控制存储的控制逻辑，所述控制逻辑用于处理包括将数据从所述输入缓冲器传送到所述存储器的指令的指令，以及使所述算术逻辑单元对由所述输入缓冲器提供的操作数执行操作的指令 至少一个存储器和输入缓冲器，将操作结果输出到至少一个存储器和输出缓冲器的指令。
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