公开(公告)号：US20090249138A1

公开(公告)日：2009-10-01

申请号：US12382466

申请日：2009-03-17

申请人： Wei Liu ,  Jeong-woo Lee

发明人： Wei Liu ,  Jeong-woo Lee

IPC分类号： H03M13/05 ,  G11C29/04 ,  G06F11/22 ,  G06F11/10

CPC分类号： H03M13/3776 ,  G06F11/1068 ,  G11C2029/0411 ,  H03M13/152 ,  H03M13/153 ,  H03M13/1545

摘要： Provided is a semiconductor memory apparatus that may use an efficient protocol between an NAND flash memory device and a controller to reduce bus traffic. The flash memory device may include a memory cell array and an error correction encoder. The memory cell array may include a plurality of pages. The error correction encoder may generate first parity data based on normal data to be written to the memory cell array, compare the first parity data and second parity data encoded with the normal data stored in the memory cell array, and check an error. The error position detector may detect an error position in response to the error signal transmitted from the error correction encoder. Thus, since the semiconductor memory apparatus may transmit and receives parity data or a syndrome between an NAND flash memory device and the controller by detecting and correcting an error in the same memory chip, bus traffic may be reduced.

摘要翻译： 提供了一种半导体存储装置，其可以使用NAND闪存器件和控制器之间的有效协议来减少总线流量。 闪存器件可以包括存储单元阵列和纠错编码器。 存储单元阵列可以包括多个页面。 误差校正编码器可以基于要写入存储单元阵列的正常数据产生第一奇偶校验数据，比较第一奇偶校验数据和存储在存储单元阵列中的通常数据编码的第二奇偶校验数据，并检查错误。 误差位置检测器可以响应于从纠错编码器发送的误差信号来检测错误位置。 因此，由于半导体存储装置可以通过检测和校正同一存储器芯片中的错误来发送和接收NAND闪存器件与控制器之间的奇偶校验数据或校正子，所以可以减少总线流量。

公开(公告)号：US08370699B2

公开(公告)日：2013-02-05

申请号：US12382466

申请日：2009-03-17

申请人： Wei Liu ,  Jeong-woo Lee

发明人： Wei Liu ,  Jeong-woo Lee

IPC分类号： G06F11/00

CPC分类号： H03M13/3776 ,  G06F11/1068 ,  G11C2029/0411 ,  H03M13/152 ,  H03M13/153 ,  H03M13/1545

摘要： Provided is a semiconductor memory apparatus that may use an efficient protocol between an NAND flash memory device and a controller to reduce bus traffic. The flash memory device may include a memory cell array and an error correction encoder. The memory cell array may include a plurality of pages. The error correction encoder may generate first parity data based on normal data to be written to the memory cell array, compare the first parity data and second parity data encoded with the normal data stored in the memory cell array, and check an error. The error position detector may detect an error position in response to the error signal transmitted from the error correction encoder. Thus, since the semiconductor memory apparatus may transmit and receives parity data or a syndrome between an NAND flash memory device and the controller by detecting and correcting an error in the same memory chip, bus traffic may be reduced.

公开(公告)号：US20050107996A1

公开(公告)日：2005-05-19

申请号：US10857023

申请日：2004-06-01

申请人： Woo-young Jang ,  Jin-ho Cho ,  Sang-hoon Shin ,  Jeong-woo Lee

发明人： Woo-young Jang ,  Jin-ho Cho ,  Sang-hoon Shin ,  Jeong-woo Lee

IPC分类号： A61B5/05 ,  A61B5/04 ,  A61B5/053 ,  G06G7/48

CPC分类号： A61B5/053

摘要： A skin impedance model of a predetermined part of a living body, which is an object to be measured, wherein the skin impedance model is estimated by providing a predetermined current between two ends of the predetermined part and measuring a voltage between the two ends, the model including a first area having a first resistor and a first constant phase element (CPE) connected in parallel, a second area having a second resistor and a second CPE connected in parallel, and a third resistor serially connected to the parallel connection of the second resistor and the second CPE, and a third area having a fourth resistor and a third CPE connected in parallel, wherein the second area and the third area are connected in parallel and are serially connected to the first area through a fifth resistor.

摘要翻译： 作为被测定对象的生物体的规定部位的皮肤阻抗模型，通过在规定部位的两端之间设置规定电流并测定两端之间的电压来推定皮肤阻抗模型， 包括具有第一电阻器和并联连接的第一恒定相位元件（CPE）的第一区域，具有并联连接的第二电阻器和第二CPE的第二区域，以及串联连接到第二电容器的并联连接的第三电阻器 电阻器和第二CPE，以及具有并联连接的第四电阻器和第三CPE的第三区域，其中第二区域和第三区域并联连接并且通过第五电阻器串联连接到第一区域。

公开(公告)号：US20120089767A1

公开(公告)日：2012-04-12

申请号：US13193638

申请日：2011-07-29

申请人： Won-chul Lee ,  Jeong-woo Lee

发明人： Won-chul Lee ,  Jeong-woo Lee

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/7204

摘要： A storage device comprises at least one nonvolatile memory and a lock mode management module. The lock mode management module places the storage device in a soft lock mode in which only predetermined writing operations are allowed, upon determining that a number of reserved blocks in a flash memory is less than or equal to a reference value.

摘要翻译： 存储装置包括至少一个非易失性存储器和锁模式管理模块。 一旦确定闪速存储器中的多个保留​​块小于或等于参考值，锁定模式管理模块将存储设备置于仅允许预定写入操作的软锁定模式。