公开(公告)号：US09117677B2

公开(公告)日：2015-08-25

申请号：US13272389

申请日：2011-10-13

申请人： Wei Yu Ma ,  Kuo-Ji Chen ,  Fang-Tsun Chu ,  Ta-Pen Guo

发明人： Wei Yu Ma ,  Kuo-Ji Chen ,  Fang-Tsun Chu ,  Ta-Pen Guo

IPC分类号： H01L27/06 ,  H01L21/768 ,  H01L27/02 ,  H01L23/522

CPC分类号： H01L27/0266 ,  H01L21/76895 ,  H01L23/5228 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present application discloses a semiconductor integrated circuit including a substrate having electrical devices formed thereon, a local interconnection layer formed over the substrate, and a global interconnection layer formed over the local interconnection layer. The local interconnection layer has a first set of conductive structures arranged to electrically connect within the individual electrical devices, among one of the electrical devices and its adjacent electrical devices, or vertically between the devices and the global interconnection layer. At least one of the first set of conductive structures is configured to have a resistance value greater than 50 ohms. The global interconnection layer has a second set of conductive structures arranged to electrically interconnect the electrical devices via the first set conductive structures.

摘要翻译： 本申请公开了一种半导体集成电路，包括其上形成有电气器件的衬底，形成在衬底上的局部互连层，以及形成在局部互连层上的全局互连层。 局部互连层具有第一组导电结构，其布置成在各个电气设备之间，电气设备及其相邻的电气设备之一中，或垂直设备和全局互连层之间电连接。 第一组导电结构中的至少一个被配置为具有大于50欧姆的电阻值。 全局互连层具有布置成经由第一组导电结构电连接电器件的第二组导电结构。

公开(公告)号：US09293606B2

公开(公告)日：2016-03-22

申请号：US13296410

申请日：2011-11-15

申请人： Kuo-Ji Chen ,  Wei Yu Ma ,  Ta-Pen Guo ,  Hsien-Wei Chen ,  Hao-Yi Tsai

发明人： Kuo-Ji Chen ,  Wei Yu Ma ,  Ta-Pen Guo ,  Hsien-Wei Chen ,  Hao-Yi Tsai

IPC分类号： H01L29/93 ,  H01L29/94 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L27/06 ,  H01L27/08 ,  H01L49/02

CPC分类号： H01L29/93 ,  H01L23/5223 ,  H01L23/5286 ,  H01L23/585 ,  H01L27/0629 ,  H01L27/0805 ,  H01L28/60 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： A seal ring for semiconductor devices is provided with embedded decoupling capacitors. The seal ring peripherally surrounds an integrated circuit chip in a seal ring area. The at least one embedded decoupling capacitor may include MOS capacitors, varactors, MOM capacitors and interdigitized capacitors with multiple capacitor plates coupled together. The opposed capacitor plates are coupled to different potentials and may advantageously be coupled to Vdd and Vss.

摘要翻译： 用于半导体器件的密封环设置有嵌入式去耦电容器。 密封环外围围绕密封环区域中的集成电路芯片。 至少一个嵌入式去耦电容器可以包括MOS电容器，变容二极管，MOM电容器和具有多个电容器板耦合在一起的叉指电容器。 相对的电容器板耦合到不同的电位，并且可以有利地耦合到Vdd和Vss。

公开(公告)号：US20120306023A1

公开(公告)日：2012-12-06

申请号：US13149547

申请日：2011-05-31

申请人： Wei Yu Ma ,  Fang-Tsun Chu ,  Kvei-Feng Yen ,  Yao-Bin Wang

发明人： Wei Yu Ma ,  Fang-Tsun Chu ,  Kvei-Feng Yen ,  Yao-Bin Wang

IPC分类号： H01L27/06 ,  H01L21/8234

CPC分类号： H01L23/5226 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76879 ,  H01L23/528 ,  H01L27/0629 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.

摘要翻译： 一种方法包括在半导体衬底的表面形成晶体管，其中形成晶体管的步骤包括形成栅电极，以及形成与栅电极相邻的源/漏区。 第一金属特征形成为至少包括与栅电极相同水平的部分。 第二金属特征同时形成，并且与第一金属特征结合并接触。 第二金属特征中的第一个被去除并被第三金属特征替换，其中第二金属特征的第二个不被去除。 直接在栅极上方形成第四金属特征，其中第三和第四金属特征使用相同的金属填充工艺形成。

公开(公告)号：US08569129B2

公开(公告)日：2013-10-29

申请号：US13149547

申请日：2011-05-31

申请人： Wei Yu Ma ,  Fang-Tsun Chu ,  Kvei-Feng Yen ,  Yao-Bin Wang

发明人： Wei Yu Ma ,  Fang-Tsun Chu ,  Kvei-Feng Yen ,  Yao-Bin Wang

IPC分类号： H01L21/8234 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/20 ,  H01L21/3205

CPC分类号： H01L23/5226 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76879 ,  H01L23/528 ,  H01L27/0629 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.

摘要翻译： 一种方法包括在半导体衬底的表面形成晶体管，其中形成晶体管的步骤包括形成栅电极，以及形成与栅电极相邻的源/漏区。 第一金属特征形成为至少包括与栅电极相同水平的部分。 第二金属特征同时形成，并且与第一金属特征结合并接触。 第二金属特征中的第一个被去除并被第三金属特征替换，其中第二金属特征的第二个不被去除。 直接在栅极上方形成第四金属特征，其中第三和第四金属特征使用相同的金属填充工艺形成。

公开(公告)号：US09124086B2

公开(公告)日：2015-09-01

申请号：US13557520

申请日：2012-07-25

申请人： Wei Yu Ma ,  Kuo-Ji Chen

发明人： Wei Yu Ma ,  Kuo-Ji Chen

IPC分类号： H02H9/04

CPC分类号： H02H9/04 ,  H02H9/046

摘要： Among other things, one or more techniques and/or systems for providing failsafe electrostatic discharge (ESD) protection are provided. In one embodiment, ESD protection is provided by connecting a voltage fail safe (VFS) supply voltage to an NWELL circuit interface (e.g., of a PMOS transistor) and connecting PAD to at least one of VFS or the NWELL circuit interface. To this end, circuitry to be protected from ESD (e.g., circuitry operably connected to PAD) is provided with failsafe ESD protection (e.g., such that a non-snapback NMOS device may be utilized to discharge ESD current, where a non-snapback NMOS generally consumes less semiconductor real estate and is less complex to produce as compared to a snapback NMOS), for example. In this manner, failsafe ESD protection is efficiently provided.

摘要翻译： 提供了一种或多种用于提供故障安全静电放电（ESD）保护的技术和/或系统。 在一个实施例中，通过将电压故障安全（VFS）电源电压连接到NWELL电路接口（例如PMOS晶体管）并将PAD连接到VFS或NWELL电路接口中的至少一个来提供ESD保护。 为此，要保护免受ESD（例如，可操作地连接到PAD的电路）的电路具有故障安全ESD保护（例如，使得可以使用非快速恢复的NMOS器件来放电ESD电流，其中非快速恢复NMOS 通常消耗更少的半导体不动产，并且与快速恢复NMOS相比，生产的复杂度较低）。 以这种方式，有效地提供故障安全ESD保护。

公开(公告)号：US08760828B2

公开(公告)日：2014-06-24

申请号：US13415621

申请日：2012-03-08

申请人： Wei Yu Ma

发明人： Wei Yu Ma

IPC分类号： H02H3/22

CPC分类号： H02H9/046

摘要： A circuit with an electro-static discharge clamp coupled to a first power source and second power source. The electro-static discharge clamp includes an NMOS stack and an electro-static discharge detector. The NMOS stack has a first NMOS transistor with gate node ng1 and a second NMOS transistor with gate node ng2. The electro-static discharge detector is configured to control the NMOS stack, and may include three switches. A first switch is configured to switch the gate node ng1 to the second power source. A second switch is configured to switch the gate node ng1 to the gate node ng2. A third switch is configured to switch the gate node ng1 to the ground.

摘要翻译： 具有耦合到第一电源和第二电源的静电放电钳的电路。 静电放电钳包括NMOS堆叠和静电放电检测器。 NMOS堆叠具有具有栅极节点ng1的第一NMOS晶体管和具有栅极节点ng2的第二NMOS晶体管。 静电放电检测器被配置为控制NMOS堆叠，并且可以包括三个开关。 第一开关被配置为将门节点ng1切换到第二电源。 第二开关被配置为将门节点ng1切换到门节点ng2。 第三开关被配置为将门节点ng1切换到地。

公开(公告)号：US20140029142A1

公开(公告)日：2014-01-30

申请号：US13557520

申请日：2012-07-25

申请人： Wei Yu Ma ,  Kou-Ji Chen

发明人： Wei Yu Ma ,  Kou-Ji Chen

IPC分类号： H02H9/04

CPC分类号： H02H9/04 ,  H02H9/046

摘要： Among other things, one or more techniques and/or systems for providing failsafe electrostatic discharge (ESD) protection are provided. In one embodiment, ESD protection is provided by connecting a voltage fail safe (VFS) supply voltage to an NWELL circuit interface (e.g., of a PMOS transistor) and connecting PAD to at least one of VFS or the NWELL circuit interface. To this end, circuitry to be protected from ESD (e.g., circuitry operably connected to PAD) is provided with failsafe ESD protection (e.g., such that a non-snapback NMOS device may be utilized to discharge ESD current, where a non-snapback NMOS generally consumes less semiconductor real estate and is less complex to produce as compared to a snapback NMOS), for example. In this manner, failsafe ESD protection is efficiently provided.

摘要翻译： 提供了一种或多种用于提供故障安全静电放电（ESD）保护的技术和/或系统。 在一个实施例中，通过将电压故障安全（VFS）电源电压连接到NWELL电路接口（例如PMOS晶体管）并将PAD连接到VFS或NWELL电路接口中的至少一个来提供ESD保护。 为此，要保护免受ESD（例如，可操作地连接到PAD的电路）的电路具有故障安全ESD保护（例如，使得可以使用非快速恢复的NMOS器件来放电ESD电流，其中非快速恢复NMOS 通常消耗更少的半导体不动产，并且与快速恢复NMOS相比，生产的复杂度较低）。 以这种方式，有效地提供故障安全ESD保护。