摘要:
A multi-phase buck converter has a digital compensator to select a set of compensation coefficients depending on the operating phase number of the multi-phase buck converter, or including different compensators for each operation phase number to improve the loop gain bandwidth, transient response and stability of the multi-phase buck converter. The multi-phase buck converter operates with more phase circuits for higher loading and operates with fewer phase circuits for lower loading. The compensation varies with the number of the operated phase circuits so to be adaptive to the operation condition with an optimized control-to-output voltage transfer function.
摘要:
An easy LSB tuning method is proposed for a digitally controlled DC-DC converter to increase the DC gain of the digitally controlled DC-DC converter under conditions of no-limit-cycle and a finite bit number to reduce steady-state error of the digitally controlled DC-DC converter. The LSB of one or more of the coefficients in the denominator of the discrete-time domain transfer function of the digital compensator in the digitally controlled DC-DC converter is so tuned that the sum of all coefficients in the denominator of the discrete-time domain transfer function becomes zero. Therefore, the influence of round-off effect on the coefficients of the digital compensator is mitigated.
摘要:
A control circuit and method for controlling a power converter comprises an adder, a digital compensator, and a pulse width modulation circuit. The adder acquires an output voltage difference between the output voltage and the reference output voltage. The digital compensator, which has a Z-domain transfer function, references the output voltage difference to generate a pulse width control signal with the least significant bits of the denominator coefficient in the Z-domain transfer function being regulated to achieve the load line function of the power converter. Further, the pulse modulation circuit is controlled by the pulse width control signal to generate the pulse width modulation signal to control ON/OFF of the power converter.
摘要:
An easy LSB tuning method is proposed for a digitally controlled DC-DC converter to increase the DC gain of the digitally controlled DC-DC converter under conditions of no-limit-cycle and a finite bit number to reduce steady-state error of the digitally controlled DC-DC converter. The LSB of one or more of the coefficients in the denominator of the discrete-time domain transfer function of the digital compensator in the digitally controlled DC-DC converter is so tuned that the sum of all coefficients in the denominator of the discrete-time domain transfer function becomes zero. Therefore, the influence of round-off effect on the coefficients of the digital compensator is mitigated.
摘要:
The present invention provides a motor controller having one or more multi-functional pins. The motor controller includes a plurality of pins but does not include a dedicated pin for transmitting a clock signal and a dedicated pin for transmitting a motor specification database setting signal, wherein the clock signal and the motor specification database setting signal are for setting motor specification data. The clock signal and the motor specification database setting signal are transmitted through two of the plural pins which are multi-functional function pins shared by other functions in a normal operation mode. In a motor specification database setting mode, these multi-functional function pins are used for transmitting the clock signal and the motor specification database setting signal. In the normal operation mode, these multi-functional function pins are used for other functions.
摘要:
The present invention provides a motor controller having one or more multi-functional pins. The motor controller includes a plurality of pins but does not include a dedicated pin for transmitting a clock signal and a dedicated pin for transmitting a motor specification database setting signal, wherein the clock signal and the motor specification database setting signal are for setting motor specification data. The clock signal and the motor specification database setting signal are transmitted through two of the plural pins which are multi-functional function pins shared by other functions in a normal operation mode. In a motor specification database setting mode, these multi-functional function pins are used for transmitting the clock signal and the motor specification database setting signal. In the normal operation mode, these multi-functional function pins are used for other functions.
摘要:
A zero-crossing detection circuit and a commutation device using the zero-crossing detection circuit are provided. The zero-crossing detection circuit is adapted into a three-phase brushless DC (direct current) motor with first to third coils. One terminal of each of the first to third coils is electrically coupled together with each other. The detection circuit comprises a first selection circuit, a second selection circuit and a comparator. The first selection circuit and the second selection circuit are both electrically coupled to another terminals of the first to third coils, to obtain first to third terminal voltages, and output one of the first to third terminal voltages according to a selection signal. The comparator is configured for comparing an output of the first selection circuit and an output of the second selection circuit, to output a comparing result.
摘要:
A zero-crossing detection circuit and a commutation device using the zero-crossing detection circuit are provided. The zero-crossing detection circuit is adapted into a three-phase brushless DC (direct current) motor with first to third coils. One terminal of each of the first to third coils is electrically coupled together with each other. The detection circuit comprises a first selection circuit, a second selection circuit and a comparator. The first selection circuit and the second selection circuit are both electrically coupled to another terminals of the first to third coils, to obtain first to third terminal voltages, and output one of the first to third terminal voltages according to a selection signal. The comparator is configured for comparing an output of the first selection circuit and an output of the second selection circuit, to output a comparing result.
摘要:
A method for designing a digital compensator for a switching mode power supply is provided such that the digital compensator has complex conjugated zero pair or a right hand pole to eliminate the complex conjugated pole pair or right hand zero in the transfer function of the control-to-output voltage of the switching mode power supply.
摘要:
For a multiphase interleaved voltage regulator, an offset cancellation circuit is applied for each phase separately. The current loop gain of each phase is thus increased to mitigate the beat-frequency oscillation in phase currents when the beat frequency is below the bandwidth of the low-pass filter in the offset cancellation circuit, without introducing additional instability issue that is the drawback of increasing current-sensing gain.